AD7701
P IN FUNCTIO N D ESCRIP TIO N
P in
Mnem onic D escription
1
MODE
Selects the Serial Interface Mode. If MODE is tied to –5 V, the AD7701 will operate in the asynchronous
communications (ac) mode. T he SCLK pin is configured as an input, and data is transmitted in two bytes,
each with one start bit and two stop bits. If MODE is tied to DGND, the synchronous external clocking
(SEC) mode is selected. SCLK is configured as an input, and the output appears without formatting, the
MSB coming first. If MODE is tied to +5 V, the AD7701 operates in the synchronous self-clocking (SSC)
mode. SCLK is configured as an output, with a clock frequency of fCLKlN/4 and 25% duty-cycle.
2
CLKOUT
Clock Output to generate an Internal Master Clock by connecting a crystal between CLKOUT and CLKIN.
If an external clock is used, CLKOUT is not connected.
3
CLKIN
Clock Input for External Clock.
4, 17
SC1, SC2
System Calibration Pins. T he state of these pins, when CAL is taken high, determines the type of calibration
performed.
5
DGND
DVSS
AVSS
AGND
AIN
Digital Ground. Ground reference for all digital signals.
Digital Negative Supply, –5 V nominal.
Analog Negative Supply, –5 V nominal.
Analog Ground. Ground reference for all analog signals.
Analog Input.
6
7
8
9
10
VREF
Voltage Reference Input, +2.5 V nominal. T his determines the value of positive full-scale in the unipolar
mode and of both positive and negative full-scale in the bipolar mode.
11
12
13
SLEEP
BP/UP
CAL
Sleep mode pin. When this pin is taken low, the AD7701 goes into a low-power mode with typically 10 µW
power consumption.
Bipolar/Unipolar Mode Pin. When this pin is low, the AD7701 is configured for a unipolar input range going
from AGND to VREF. When Pin 12 is high, the AD7701 is configured for a bipolar input range, ±VREF
.
Calibration Mode Pin. When CAL is taken high for more than 4 cycles, the AD7701 is reset and performs a
calibration cycle when CAL is brought low again. T he CAL pin can also be used as a strobe to synchronize
the operation of several AD7701s.
14
15
16
AVDD
DVDD
CS
Analog Positive Supply, +5 V nominal.
Digital Positive Supply, +5 V nominal.
Chip Select Input. When CS is brought low, the AD7701 will begin to transmit serial data in a format deter-
mined by the state of the MODE pin.
18
19
20
DRDY
SCLK
Data Ready output. DRDY is low when valid data is available in the output register. It goes high after transmission
of a word is completed. It also goes high for four clock cycles when a new data word is being loaded into the out-
put register, to indicate that valid data is not available, irrespective of whether data transmission is complete or not.
Serial Clock Input/Output. T he SCLK pin in configured as an input or output, dependent on the type of se-
rial data transmission that has been selected by the MODE pin. When configured as an output in the syn-
chronous self-clocking mode, it has a frequency of fCLKIN/4 and a duty cycle of 25%.
SDAT A
Serial Data Output. T he AD7701’s output data is available at this pin as a 16-bit serial word. T he transmis-
sion format is determined by the state of the MODE pin.
O RD ERING GUID E
P IN CO NFIGURATIO NS
D IP , Cer dip, SO IC
SSO P
Tem perature
Linearity
P ackage
Model
Range
Error (% FSR) O ptions*
20
1
2
1
2
MODE
SDATA
28
27
26
25
24
23
22
21
MODE
SDATA
SCLK
19 SCLK
CLKOUT
CLKOUT
AD7701AN
AD7701BN
AD7701AR
AD7701BR
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
0.003
0.0015
0.003
0.0015
0.003
0.003
0.0015
N-20
N-20
R-20
R-20
RS-28
Q-20
Q-20
Q-20
Q-20
3
18
3
DRDY
CLKIN
SC1
DRDY
SC2
CS
CLKIN
SC1
17
4
4
SC2
AD7701
TOP VIEW
16
5
5
CS
DGND
DVSS
AVSS
DGND
NC
15
6
6
DVDD
NC
(Not to Scale)
AD7701
14 AVDD
7
7
NC
NC
NC
AD7701ARS –40°C to +85°C
TOP VIEW
(Not to Scale)
13
8
8
DV
SS
CAL
AGND
AIN
AD7701AQ
AD7701BQ
AD7701SQ
AD7701T Q
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C 0.003
–55°C to +125°C 0.0015
12
9
20 DV
19 AV
9
NC
BP/UP
DD
DD
AV
SS
11
VREF
10
10
SLEEP
18
NC 11
12
NC
17
CAL
AGND
16
15
A
13
14
BP/UP
SLEEP
IN
NOT ES
V
REF
*N = Plastic DIP; Q = Cerdip; R = SOIC; RS = SSOP.
NC = NO CONNECT
–4–
REV. D