AD7701
The output settling of the AD7701 in response to a step input
change is shown in Figure 12. The Gaussian response has fast
settling with no overshoot, and the worst-case settling time to
±
0.0007% (± 0.5 LSB) is 125 ms with a 4.096 MHz master
clock frequency.
The input sampling frequency, output data rate, filter character-
istics and calibration time are all directly related to the master
clock frequency f
CLKIN
by the ratios given in the specification
table. Therefore, the first step in system design with the
AD7701 is to select a master clock frequency suitable for the
bandwidth and output data rate required by the application.
ANALOG INPUT RANGES
The AD7701 performs conversion relative to an externally
supplied reference voltage, which allows easy interfacing to
ratiometric systems. In addition, either unipolar or bipolar input
voltage range may be selected using the BP/UP input. With BP/
UP
tied low, the input range is unipolar and the span is 0 to
+V
REF
. With BP/UP tied high, the input range is bipolar and the
span is
±
V
REF
. In the bipolar mode both positive and negative
full scale are directly determined by V
REF
. This offers superior
tracking of positive and negative full scale and better midscale
(bipolar zero) stability than bipolar schemes that simply scale
and offset the input range.
The digital output coding for the unipolar range is Unipolar
Binary; for the bipolar range it is Offset Binary. Bit weights for
the unipolar and bipolar modes are shown in Table I. The input
voltages and output codes for unipolar and bipolar ranges, using
the recommended +2.5 V reference, are shown in Table II.
Table I. Bit Weight Table (2.5 V Reference Voltage)
100
PERCENT OF FINAL VALUE
80
60
40
20
0
0
40
80
TIME – ms
120
160
Figure 12. AD7701 Step Response
USING THE AD7701
SYSTEM DESIGN CONSIDERATIONS
The AD7701 operates differently from successive approxima-
tion ADCs or other integrating ADCs. Since it samples the sig-
nal continuously, like a tracking ADC, there is no need for a
start convert command. The 16-bit output register is updated at
a 4 kHz rate, and the output can be read at any time, either syn-
chronously or asynchronously.
CLOCKING
Unipolar Mode
V
10
19
38
76
153
LSBs
0.26
0.5
1.00
2.00
4.00
% FS
0.0004
0.0008
0.0015
0.0031
0.0061
ppm FS
4
8
15
31
61
Bipolar Mode
LSBs % FS
0.13
0.26
0.5
1.00
2.00
0.0002
0.0004
0.0008
0.0015
0.0031
ppm FS
2
4
8
15
31
The AD7701 requires a master clock input, which may be an
external TTL/CMOS compatible clock signal applied to the
CLKIN pin (CLKOUT not used). Alternatively, a crystal of the
correct frequency can be connected between CLKIN and
CLKOUT, when the clock circuit will function as a crystal-
controlled oscillator.
Table II. Output Coding
Unipolar Mode
Input Relative to
FS and AGND
+V
REF
– 1.5 LSB
+V
REF
– 2.5 LSB
+V
REF
– 3.5 LSB
+V
REF
/2 + 0.5 LSB
+V
REF
/2 – 0.5 LSB
+V
REF
/2 – 1.5 LSB
AGND + 2.5 LSB
AGND + 1.5 LSB
AGND + 0.5 LSB
Input in Volts
Bipolar Mode
Input Relative to
FS and AGND
+V
REF
– 1.5 LSB
+V
REF
– 2.5 LSB
+V
REF
– 3.5 LSB
AGND + 0.5 LSB
AGND – 0.5 LSB
AGND – 1.5 LSB
Input in Volts
Output Data
1111 1111 1111 1111
1111 1111 1111 1110
1111 1111 1111 1101
1111 1111 1111 1100
1000 0000 0000 0001
1000 0000 0000 0000
0111 1111 1111 1111
0111 1111 1111 1110
0000 0000 0000 0011
0000 0000 0000 0010
0000 0000 0000 0001
0000 0000 0000 0000
+2.499943
+2.499905
+2.499867
+2.499886
+2.499810
+2.499733
+1.250019
+1.249981
+1.249943
+0.000038
–0.000038
–0.000114
+0.000095
+0.000057
+0.000019
–V
REF
+ 2.5 LSB
–V
REF
+ 1.5 LSB
–V
REF
+ 0.5 LSB
–2.499810
–2.499886
–2.499962
NOTES
1
V
REF
= +2.5 V
2
AGND = 0 V
3
Unipolar Mode, 1 LSB = 2.5 V/655536 = 0.000038 V
4
Bipolar Mode, 1 LSB = 5 V/65536 = 0.000076 V
5
Inputs are voltages at code transitions.
REV. D
–9–
AD [ ANALOG DEVICES ]
