AD7701
Sigma-delta ADCs are generally described by the order of the
analog low-pass filter. A simple example of a first order sigma-
delta ADC is shown in Figure 9. T his contains only a first-order
low-pass filter or integrator. It also illustrates the derivation of
the alternative name for these devices: Charge-Balancing ADCs.
FILTER CH ARACTERISTICS
T he cutoff frequency of the digital filter is fCLK /409600. At the
maximum clock frequency of 4.096 MHz, the cutoff frequency
of the filter is 10 Hz and the output rate is 4 kHz.
Figure 10 shows the filter frequency response. T his is a 6-pole
Gaussian response that provides 55 dB of 60 Hz rejection for a
10 Hz cutoff frequency. If the clock frequency is halved to give a
5 Hz cutoff, 60 Hz rejection is better than 90 dB. A normalized
s-domain pole-zero plot of the filter is shown in Figure 11.
C
CLOCK
R
A
IN
TO DIGITAL
FILTER
T he response of the filter is defined by:
INTEGRATOR
H(x) = [1+ 0.693x2 + 0.240x4 + 0.0555x6 + 0.00962x8
STROBED
COMPARATOR
–0.5
+ 0.00133x10 + 0.000154x12]
R
where:
+V
–V
REF
x = f/f3 dB, f3 dB = fCLKIN/409600,
and
REF
1-BIT DAC
f is the frequency of interest.
Figure 9. SEC Basic Charge-Balancing ADC
20
T he term charge-balancing comes from the fact that this system
is a negative feedback loop that tries to keep the net charge on
the integrator capacitor at zero, by balancing charge injected by
the input voltage with charge injected by the 1-bit DAC. When
the analog input is zero, the only contribution to the integrator
output comes from the 1-bit DAC. For the net charge on the
integrator capacitor to be zero, the DAC output must spend half
its time at +1 V and half its time at –1 V. Assuming ideal
components, the duty cycle of the comparator will be 50%.
0
f
= 4MHz
CLK
–20
–40
–60
f
= 2MHz
CLK
–80
–100
–120
When a positive analog input is applied, the output of the 1-bit
DAC must spend a larger proportion of the time at +1 V, so the
duty cycle of the comparator increases. When a negative input
voltage is applied, the duty cycle decreases.
f
= 1MHz
CLK
–140
–160
1
100
10
FREQUENCY – Hz
T he AD7701 uses a second-order sigma-delta modulator and a
sophisticated digital filter that provides a rolling average of the
sampled output. After power-up or if there is a step change in
the input voltage, there is a settling time that must elapse before
valid data is obtained.
Figure 10. Frequency Response of AD7701 Filter
jw
j2
j1
D IGITAL FILTERING
S1,2 = –1.4663 + j1.8191
T he AD7701’s digital filter behaves like a similar analog filter,
with a few minor differences.
s
S3,4 = –1.7553 + j1.0005
S5,6 = –1.8739 + j0.32272
0
–2
–1
First, since digital filtering occurs after the A to D conversion
process, it can remove noise injected during the conversion
process. Analog filtering cannot do this.
–j1
–j2
On the other hand, analog filtering can remove noise super-
imposed on the analog signal before it reaches the ADC. Digital
filtering cannot do this and noise peaks riding on signals near
full scale have the potential to saturate the analog modulator
and digital filter, even though the average value of the signal is
within limits. T o alleviate this problem, the AD7701 has over-
range headroom built into the sigma-delta modulator and digital
filter which allows overrange excursions of 100 mV. If noise
signals are larger than this, consideration should be given to
analog input filtering, or to reducing the gain in the input
channel so that a full-scale input (2.5 V) gives only a half-scale
input to the AD7701 (1.25 V). T his will provide an overrange
capability greater than 100% at the expense of reducing the
dynamic range by 1 bit (50%).
Figure 11. Norm alized Pole-Zero Plot of AD7701 Filter
Since the AD7701 contains this on-chip, low-pass filtering,
there is a settling time associated with step function inputs, and
data will be invalid after a step change until the settling time has
elapsed. T he AD7701 is therefore unsuitable for high speed
multiplexing, where channels are switched and converted se-
quentially at high rates, as switching between channels can
cause a step change in the input. Rather, it is intended for dis-
tributed converter systems using one ADC per channel.
However, slow multiplexing of the AD7701 is possible, provided
that the settling time is allowed to elapse before data for the new
channel is accessed.
–8–
REV. D
ADI [ ADI ]
