AD73360L
t1
80
70
60
50
40
30
20
10
0
t2
t3
Figure 1. MCLK Timing
100A
I
OL
TO OUTPUT
PIN
2.1V
–10
C
15pF
L
–85 –75
–65
–55
–45
–35
– dBm0
–25
–15
–5
5
3.17
V
IN
100A
I
OH
Figure 5. S/(N+D) vs. VIN (ADC @ 3 V) Over Voiceband
Bandwidth (300 Hz–3.4 kHz)
Figure 2. Load Circuit for Timing Specifications
t2
t1
t3
MCLK
t13
t5
t6
SCLK*
t4
* SCLK IS INDIVIDUALLY PROGRAMMABLE
IN FREQUENCY (MCLK/4 SHOWN HERE).
Figure 3. SCLK Timing
SE (I)
THREE-
STATE
SCLK (O)
SDIFS (I)
t7
t8
t8
t7
SDI (I)
D15
D14
D1
D0
D15
t9
t10
THREE-
STATE
SDOFS (O)
t11
t12
THREE-
STATE
SDO (O)
D15
D2
D1
D0
D15
D14
Figure 4. Serial Port (SPORT)
–4–
REV. 0
ADI [ ADI ]
