AD73360L
t
1
t
2
70
60
50
S/(N+D) – dB
2.1V
80
t
3
40
30
20
Figure 1. MCLK Timing
100 A
I
OL
10
0
TO OUTPUT
PIN
C
L
15pF
100 A
I
OH
–10
–85
–75
–65
–55
–45
–35
V
IN
– dBm0
–25
–15
–5
5
3.17
Figure 5. S/(N+D) vs. V
IN
(ADC @ 3 V) Over Voiceband
Bandwidth (300 Hz–3.4 kHz)
Figure 2. Load Circuit for Timing Specifications
t
1
MCLK
t
2
t
3
t
13
SCLK*
t
5
t
4
t
6
*
SCLK IS INDIVIDUALLY PROGRAMMABLE
IN FREQUENCY (MCLK/4 SHOWN HERE).
Figure 3. SCLK Timing
SE (I)
SCLK (O)
THREE-
STATE
t
7
SDIFS (I)
t
8
t
7
SDI (I)
THREE-
SDOFS (O) STATE
THREE-
STATE
D15
D14
D1
D0
t
8
D15
t
9
t
10
t
12
D15
t
11
D2
D1
D0
D15
D14
SDO (O)
Figure 4. Serial Port (SPORT)
–4–
REV. 0