AD73360L
Parameter
LOGIC OUTPUT
V
OH
, Output High Voltage
V
OL
, Output Low Voltage
Three-State Leakage Current
POWER SUPPLIES
AVDD1, AVDD2
DVDD
I
DD8
AD73360LA
Min
Typ
Max
V
DD
– 0.4
0
–10
2.7
2.7
V
DD
0.4
+10
3.6
3.6
Unit
V
V
µA
V
V
See Table I
Test Conditions/Comments
|IOUT|
≤
100
µA
|IOUT|
≤
100
µA
NOTES
1
Operating temperature range is as follows: –40°C to +85°C. Therefore, T
MIN
= –40°C and T
MAX
= +85°C.
2
Test conditions: Input PGA set for 0 dB gain (unless otherwise noted).
3
At input to sigma-delta modulator of ADC.
4
Guaranteed by design.
5
Overall group delay will be affected by the sample rate and the external digital filtering.
6
The ADC’s input impedance is inversely proportional to DMCLK and is approximated by: (4
×
10
11
)/DMCLK.
7
Frequency response of ADC measured with input at audio reference level (the input level that produces an output level of –10 dBm0), with 38 dB preamplifier
bypassed and input gain of 0 dB.
8
Test Conditions: no load on digital inputs, analog inputs ac-coupled to ground.
Specifications subject to change without notice.
Table I. Current Summary (AVDD = DVDD = 3.3 V)
Conditions
ADCs Only On
REFCAP Only On
REFCAP and REFOUT Only On
All Sections On
All Sections Off
All Sections Off
Total
Current
(Max)
25
1.0
3.5
26.5
1.0
0.05
SE
1
0
0
1
0
0
MCLK
ON
Yes
No
No
Yes
Yes
No
Comments
REFOUT Disabled
REFOUT Disabled
REFOUT Enabled
MCLK Active Levels Equal to 0 V and DVDD
Digital Inputs Static and Equal to 0 V or DVDD
The above values are in mA and are typical values unless otherwise noted. MCLK = 16.384 MHz; SCLK = 16.384 MHz.
TIMING CHARACTERISTICS
Parameter
Clock Signals
t
1
t
2
t
3
Serial Port
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
11
t
12
t
13
(AVDD = 2.7 V to 3.6 V; DVDD = 2.7 V to 3.6 V; AGND = DGND = 0 V; T
A
= T
MlN
to T
MAX
, unless other-
wise noted.)
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns max
ns max
ns max
Description
See Figure 1.
MCLK Period
MCLK Width High
MCLK Width Low
See Figures 3 and 4.
SCLK Period
SCLK Width High
SCLK Width Low
SDI/SDIFS Setup before SCLK Low
SDI/SDIFS Hold after SCLK Low
SDOFS Delay from SCLK High
SDOFS Hold after SCLK High
SDO Hold after SCLK High
SDO Delay from SCLK High
SCLK Delay from MCLK
Limit at
T
A
= –40 C to +85 C
61
24.4
24.4
t
1
0.4
×
t
1
0.4
×
t
1
20
0
10
10
10
10
30
REV. 0
–3–
AD [ ANALOG DEVICES ]
