AD73360
80
70
60
50
40
30
20
10
0
t1
t2
t3
Figure 1. MCLK Timing
100A
I
OL
–10
–85 –75
–65
–55
–45
–35
–25
–15
–5
5
TO OUTPUT
PIN
3.17
V
– dBm0
+2.1V
IN
C
L
15pF
Figure 5a. S/(N+D) vs. VIN (ADC @ 3 V) Over Voiceband
Bandwidth (300 Hz–3.4 kHz)
I
100A
OH
80
70
60
50
40
30
20
10
0
Figure 2. Load Circuit for Timing Specifications
t2
t1
t3
MCLK
SCLK*
t13
t5
t6
t4
* SCLK IS INDIVIDUALLY PROGRAMMABLE
IN FREQUENCY (MCLK/4 SHOWN HERE).
–10
–85
–75
–65
–55
–45
–35
–25
–15
–5
5
3.17
V
– dBm0
IN
Figure 3. SCLK Timing
Figure 5b. S/(N+D) vs. VIN (ADC @ 5 V) Over Voiceband
Bandwidth (300 Hz–3.4 kHz)
SE (I)
THREE-
STATE
SCLK (O)
SDIFS (I)
t7
t8
t8
t7
SDI (I)
D15
D14
D1
D0
D15
t9
t10
THREE-
STATE
SDOFS (O)
t11
t12
THREE-
STATE
SDO (O)
D15
D2
D1
D0
D15
D14
Figure 4. Serial Port (SPORT)
REV. B
–7–
ADI [ ADI ]
