AD712
Where
1mV
100
90
5V
ω
O
= unity-gain frequency of the op amp.
2
π
SUMMING
JUNCTION
G
N
= noise gain of circuit
⎛
1
+
R
⎞
.
⎟
⎜
⎟
⎜
⎝
R
O
⎠
0V
10
0%
00823-030
This equation can then be solved for C
f
OUTPUT
C
X
=
500ns
–10V
RC
X
ω
O
+
(
1
−
G
N
)
2
−
G
N
+
2
R
ω
O
R
ω
O
(2)
Figure 30. Settling Characteristics for AD712 with AD565A,
Full-Scale Negative Transition
1mV
100
90
5V
In these equations, Capacitance C
X
is the total capacitance
appearing at the inverting terminal of the op amp. When
modeling a DAC buffer application, the Norton equivalent
circuit shown in Figure 32 can be used directly; Capacitance C
X
is the total capacitance of the output of the DAC plus the input
capacitance of the op amp (because the two are in parallel).
+
1/2
AD712
–
SUMMING
JUNCTION
V
OUT
C
F
R
R
L
C
L
0V
OUTPUT
10
0%
–10V
500ns
00823-031
Figure 32. Simplified Model of the AD712 Used as a Current-Out DAC Buffer
Figure 31. Settling Characteristics for AD712 with AD565A,
Full-Scale Positive Transition
OP AMP SETTLING TIME—A MATHEMATICAL
MODEL
The design of the AD712 gives careful attention to optimizing
individual circuit components; in addition, a careful trade-off
was made: the gain bandwidth product (4 MHz) and slew rate
(20 V/μs) were chosen to be high enough to provide very fast
settling time but not too high to cause a significant reduction
in phase margin (and therefore, stability). Thus designed, the
AD712 settles to ±0.01%, with a 10 V output step, in under 1 μs,
while retaining the ability to drive a 250 pF load capacitance
when operating as a unity-gain follower.
If an op amp is modeled as an ideal integrator with a unity-gain
crossover frequency of
ω
O
/2π, then Equation 1 accurately
describes the small signal behavior of the circuit of Figure 32,
consisting of an op amp connected as an I-to-V converter at the
output of a bipolar or CMOS DAC. This equation would com-
pletely describe the output of the system if not for the finite slew
rate and other nonlinear effects of the op amp.
V
O
−
R
=
I
IN
R
(
C
X
)
2
⎛
G
N
s
+⎜
⎜ ω +
RC
f
ω
O
⎝
O
⎞
⎟
s
+
1
⎟
⎠
When R
O
and I
O
are replaced with their Thevenin V
IN
and R
IN
equivalents, the general-purpose inverting amplifier shown in
Capacitance C
X
is either the input capacitance of the op amp, if
a simple inverting op amp is being simulated, or the combined
capacitance of the DAC output and the op amp input if the
DAC buffer is being modeled.
+
1/2
AD712
–
R
IN
V
IN
C
X
V
OUT
C
F
R
00823-033
R
L
C
L
Figure 33. Simplified Model of the AD712 Used as an Inverter
(1)
In either case, Capacitance C
X
causes the system to go from a
one-pole to a two-pole response; this additional pole increases
settling time by introducing peaking or ringing in the op amp
output. Because the value of C
X
can be estimated with reasonable
accuracy, Equation 2 can be used to choose a small capacitor
(C
F
) to cancel the input pole and optimize amplifier response.
with R = 4 kΩ.
Rev. G | Page 12 of 20
00823-032
I
O
R
O
C
X
AD [ ANALOG DEVICES ]
