AD712
60
5V
50
100
90
40
G
N
= 4.0
C
X
30
G
N
= 3.0
G
N
= 2.0
G
N
= 1.5
10
0%
20
10
5mV
60
00823-034
500ns
0
0
10
20
30
C
F
40
50
Figure 34. Value of Capacitor C
F
vs. Value of C
X
Figure 36. Settling Characteristics 0 V to −10 V Step
Upper Trace: Output of AD712 Under Test (5 V/Div)
Lower Trace: Amplified Error Voltage (0.01%/Div)
The photos of Figure 35 and Figure 36 show the dynamic
response of the AD712 in the settling test circuit of Figure 37.
5V
100
90
The input of the settling time fixture is driven by a flat top pulse
generator. The error signal output from the false summing node
of A1 is clamped, amplified by A2, and then clamped again. The
error signal is thus clamped twice: once to prevent overloading
Amplifier A2 and then a second time to avoid overloading the
oscilloscope preamp. The Tektronix oscilloscope preamp type
7A26 was carefully chosen because it does not overload with
these input levels. Amplifier A2 needs to be a very high speed
FET-input op amp; it provides a gain of 10, amplifying the error
signal output of A1.
10
0%
5mV
500ns
Figure 35. Settling Characteristics 0 V to +10 V Step
Upper Trace: Output of AD712 Under Test (5 V/Div)
Lower Trace: Amplified Error Voltage (0.01%/Div)
00823-035
5pF
HP2835
+
1/2
AD712
–
0.47µF
0.47µF
205Ω
V
ERROR ×
5
TEKTRONIX 7A26
OSCILLOSCOPE
PREAMP
INPUT SECTION
20pF
1MΩ
HP2835
4.99kΩ
DATA
DYNAMICS
5109
V
IN
10kΩ
200Ω
4.99kΩ
5 TO 18pF
–15V +15V
10kΩ
1.1kΩ
0.2 TO 0.6pF
10kΩ
AD712
5kΩ
0.1µF
(OR EQUIVALENT
FLAT TOP PULSE
GENERATION)
1/2
V
OUT
10pF
0.1µF
–15V +15V
Figure 37. Settling Time Test Circuit
Rev. G | Page 13 of 20
00823-037
00823-036
G
N
= 1.0
–
+
AD [ ANALOG DEVICES ]
