AD7008
A 3.5" floppy disk containing software to control the AD7008 is
provided with the AD7008/PCB. This software was developed
using C. The C source code is provided in a file named
A:\AD7008.C, which the user may view, run, or modify.
Controlling the AD7008/PCB
The AD7008/PCB is designed to allow control (frequency
specification, reset, etc.) through the parallel printer port of a
standard IBM-compatible PC. The user simply disconnects the
printer cable from the printer and inserts it into edge connector
P1 of the evaluation board.
An executable version of this software is also provided, and can
be executed from DOS by typing “A:\AD7008.” The software
prompts the user to provide the necessary information needed
by the program. Additional information is included in a test file
named A:\readme.txt.
The printer port provides information to the AD7008/PCB
through eight data lines and four control lines. Control signals
are latched on the AD7008/PCB to prevent problems with long
printer cables.
A windows 3.1 executable called WIN7008 is also included.
U1
DUT7008P
6
C36DRPF
P1
10k
10PB+5
RZ1
19
D0
D1
D2
D0
VREF
VREF
C7
20
21
1
2
3
4
D1
D2
LATCH
5
SMB
IOUT
2
3
4
D0
D1
COMP
D0
D1
22
23
0.1µF
D3
D4
D3
D4
R4
50
C6
0.1µF
D2
D3
D2
D3
24
25
5
5
6
7
8
9
+5V
D5
D6
D5
D6
2
1
6
IOUT
IOUT
D4
D5
D6
D7
D4
D5
D6
D7
26
8
9
SMB
SCLK
7
8
9
10
11
12
13
D7
D8
D9
D10
D7
SMB
IOUT
R5
50
10
11
12
13
10
R1
10k
D11
D12
D13
FSADJ
4
SMB
SDATA
FSADJUST
390
14
15
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
D14
D15
+5VD
RESET
C2
0.1µF
C3
0.1µF
C4
0.1µF
C5
0.1µF
16
27
32
33
34
3
R2
10k
WR
+5V
+5V
+5V
+5V
LWR
VAA
VDD
VDD
17
28
39
CS
SMB
D0
D1
D2
TC0
TC1
TC2
FSELECT
P2
PCTB2
VDD
1
2
35
36
41
42
31
+5V
R3
10k
TC3
D3
LLOAD
44
7
LOAD
AGND
DGND
DGND
DGND
DGND
C1
10µF
C8
0.1µF
SCLK
SDATA
FSELECT
18
29
SMB
CLK
U2
74HC74
+5V
2
30
38
37
43
4
PR
CLK
R6
50
H3M
LK1
5
RESET
SLEEP
RESET
+5V
LOAD
D
Q
LLOAD
40
TEST
3
OPTIONAL
1
2
3
>
C
Q
CL
6
4.7k
6PB+5
RZ2
1
XTAL1
14
VCC
OUT
+5V
+5V
GND
+5V
LOAD
U2
74HC74
10
2
3
4
5
6
C9
LATCH
RESET
12
PR
9
8
0.1µF
8
Q
WR
D
L
WR
11
LOAD
WR
VEE
>
C
LATCH
Q
CL
7
WR
13
+5V
Figure 36.
INPUTS/OUTPUTS
Description
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
Name
44-Pin PLCC (P-44A)
P1
36-pin edge connector to connect to parallel
port of PC.
0.180 (4.57)
0.165 (4.19)
0.056 (1.42)
0.042 (1.07)
0.048 (1.21)
0.042 (1.07)
CLOCK
FSEL
CMOS input for clock R6 provides termination.
CMOS input to select between Freq 0 and Freq 1.
Low selects Freq 0.
0.025 (0.63)
0.015 (0.38)
0.048 (1.21)
0.042 (1.07)
6
40
39
7
PIN 1
IDENTIFIER
0.050
(1.27)
BSC
0.63 (16.00)
0.59 (14.99)
SDATA
SCLK
IOUT
CMOS input for serial input pin.
CMOS input for clocking in SDATA.
Analog output.
0.021 (0.53)
0.013 (0.33)
TOP VIEW
(PINS DOWN)
IOUT
N
Complementary analog output.
Test point for VREF pin.
0.032 (0.81)
0.026 (0.66)
VREF
17
29
28
18
P2
LK1
+5 V and ground power connection.
External sleep command input.
0.040 (1.01)
0.025 (0.64)
0.020
(0.50)
R
0.656 (16.66)
0.650 (16.51)
SQ
SQ
0.110 (2.79)
0.085 (2.16)
0.695 (17.65)
0.685 (17.40)
–16–
REV. B
ADI [ ADI ]
