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AD7008JP50 参数 Datasheet PDF下载

AD7008JP50图片预览
型号: AD7008JP50
PDF下载: 下载PDF文件 查看货源
内容描述: CMOS DDS调制器 [CMOS DDS Modulator]
分类和应用: 数据分配系统
文件页数/大小: 16 页 / 507 K
品牌: ADI [ ADI ]
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AD7008–Typical Performance Characteristics  
REF 5.0 dBm  
10 dB/DIV  
OFFSET 4 500 000.0 Hz  
–54.7 dB  
REF 5.0 dBm  
10 dB/DIV  
OFFSET 500 000.0 Hz  
–44.8 dB  
RANGE 5.0 dBm  
RANGE 5.0 dBm  
START 0 Hz  
RBW 3 kHz  
STOP 25 000 000.0 Hz  
ST 5.6 SEC  
CENTER 16 500 000.0 Hz  
RBW 3 kHz  
SPAN 25 000 000.0 Hz  
ST 5.6 SEC  
VBW 10 kHz  
VBW 10 kHz  
Figure 32. fCLK = 50 MHz, fOUT = 16.5 MHz  
Figure 29. fCLK = 50 MHz, fOUT = 9.1 MHz  
REF 5.0 dBm  
10 dB/DIV  
OFFSET 11 100 000.0 Hz  
–54.1 dB  
RANGE 5.0 dBm  
130  
120  
110  
100  
90  
80  
70  
60  
50  
START 0 Hz  
RBW 3 kHz  
STOP 25 000 000.0 Hz  
ST 5.6 SEC  
VBW 10 kHz  
0
10  
20  
30  
40  
50  
MASTER CLOCK – MHz  
Figure 33. Typical Current Consumption vs. Frequency  
Figure 30. fCLK = 50 MHz, fOUT = 11.1 MHz  
REF 5.0 dBm  
10 dB/DIV  
OFFSET 10 675 000.0 Hz  
–47.0 dB  
RANGE 5.0 dBm  
–40  
–45  
–50  
–55  
–60  
–65  
–70  
–75  
CENTER 13 100 000.0 Hz  
RBW 3 kHz  
SPAN 25 000 000.0 Hz  
ST 5.6 SEC  
0
10  
20  
30  
40  
50  
VBW 10 kHz  
MASTER CLOCK – MHz  
Figure 34. Typical Plot of SFDR vs. Master Clock Frequency  
When fOUT = 1/3fCLK, Frequency Word = 5671C71C Hex  
Figure 31. fCLK = 50 MHz, fOUT = 13.1 MHz  
–14–  
REV. B