AD6620
TIMING CHARACTERISTICS (C
LOAD = 40 pF All Outputs)
Test
Level
AD6620AS
Typ
Parameter (Conditions)
Temp
Min
Max
Unit
CLK Timing Requirements:
tCLK
CLK Period
Full
Full
Full
Full
I
I
IV
IV
14.931
15.4
7.0
ns
ns
ns
ns
tCLK
tCLKL
tCLKH
CLK Period
CLK Width Low
CLK Width High
0.5 × tCLK
0.5 × tCLK
7.0
Reset Timing Requirements:
tRESL
RESET Width Low
Full
I
30.0
ns
Input Data Timing Requirements:
tSI
Input2 to CLK Setup Time
Full
Full
IV
IV
–1.0
6.5
ns
ns
tHI
Input2 to CLK Hold Time
Parallel Output Switching Characteristics:
tDPR
tDPF
tDPR
tDPF
tDPR
tDPF
tDPR
tDPF
CLK to OUT[15:0] Rise Delay
Full
Full
Full
Full
Full
Full
Full
Full
IV
IV
IV
IV
IV
IV
IV
IV
8.0
7.5
6.5
5.5
7.0
6.0
7.0
5.5
19.5
19.5
19.0
11.5
19.5
13.5
19.5
13.5
ns
ns
ns
ns
ns
ns
ns
ns
CLK to OUT[15:0] Fall Delay
CLK to DVOUT Rise Delay
CLK to DVOUT Fall Delay
CLK to IQOUT Rise Delay
CLK to IQOUT Fall Delay
CLK to ABOUT Rise Delay
CLK to ABOUT Fall Delay
SYNC Timing Requirements:
tSY
tHY
SYNC3 to CLK Setup Time
SYNC3 to CLK Hold Time
Full
Full
IV
IV
–1.0
6.5
ns
ns
SYNC Switching Characteristics:
tDY
CLK to SYNC4 Delay Time
Full
V
7.0
23.5
ns
Serial Input Timing:
tSSI
SDI to SCLKt Setup Time
Full
Full
Full
Full
Full
IV
IV
IV
IV
IV
1.0
2.0
4.0
1.0
2.0
ns
ns
ns
ns
ns
tHSI
tHSRF
tSSF
tHSF
SDI to SCLKtHold Time
SDFS to SCLKuHold Time
SDFS to SCLKt Setup Time5
SDFS to SCLKtHold Time5
Serial Frame Output Timing:
tDSE
SCLKuto SDFE Delay Time
Full
Full
Full
IV
V
IV
3.5
4.5
11.0
11.0
ns
ns
ns
tSDFEH
tDSO
SDFE Width High
SCLKuto SDO Delay Time
tSCLK
SCLK Switching Characteristics, SBM = “1”:
tSCLK
SCLK Period4
Full
Full
Full
Full
I
2 × tCLK
ns
ns
ns
ns
tSCLKL
tSCLKH
tSCLKD
SCLK Width Low
SCLK Width High
CLK to SCLK Delay Time
V
V
V
0.5 × tSCLK
0.5 × tSCLK
6.5
1.0
13.0
4.0
Serial Frame Timing, SBM = “1”:
tDSF
tSDFSH
SCLKu to SDFS Delay Time
SDFS Width High
Full
Full
IV
V
ns
ns
tSCLK
SCLK Timing Requirements, SBM = “0”:
tSCLK
SCLK Period
Full
Full
Full
I
IV
IV
15.4
0.4 × tSCLK
0.4 × tSCLK
ns
ns
ns
tSCLKL
tSCLKH
SCLK Width Low
SCLK Width High
0.5 × tSCLK
0.5 × tSCLK
NOTES
1This specification valid for VDD >= 3.3 V. tCLKL and tCLKH still apply.
2Specification pertains to: IN[15:0], EXP[2:0], A/B.
3Specification pertains to: SYNC_NCO, SYNC_CIC, SYNC_RCF.
4SCLK period will be ≥ 2 × tCLK when AD6620 is Serial Bus Master (SBM = 1) depending on the SDIV word.
5SDFS setup and hold time must be met, even when configured as outputs, since internally the signal is sampled at the pad.
Specifications subject to change without notice.
REV. A
–5–
ADI [ ADI ]
