AD6620
TIMING DIAGRAMS
CLK, INPUTS, PARALLEL OUTPUTS
SYNC PULSES: SLAVE OR MASTER
RESET with PAR/SER = “1” establishes Parallel Outputs active.
CLK
tCLK
tCLKH
tHY
tSY
SYNC NCO
SYNC CIC
SYNC RCF
CLK
tCLKL
NOTE:
IN THE SLAVE MODE WITH SINGLE CHANNEL OPERATION, THE WIDTH
OF THE SYNC_NCO SHOULD BE ONE SAMPLE CLOCK CYCLE. IN DUAL
CHANNEL MODE, THE PULSEWIDTH SHOULD BE TWO SAMPLE CLOCK
CYCLES. IF A PULSE LONGER THAN SPECIFIED IS USED, THE NCO WILL
BE INHIBITED AND NOT INCREMENT PROPERLY.
Figure 3. CLK Timing Requirements
Figure 6. SYNC Slave Timing Requirements
CLK
tHI
tSI
tCLK
tCHP
tCPL
IN[15:0]
EXP[2:0]
A/B
CLK
DATA
tCS
Figure 4. Input Data Timing Requirements
tCH
IN[15:0]
E[2:0]
N+1
N
tDPR
tDPF
tDPF
A/B
CLK
Figure 7. SYNC Master Delay
DV
VALID OUTPUT DATA
OUT
I/Q
Q
Q
Q
I
I
OUT
I
I
Q
B
OUT[15:0]
A
A
B
RESET
Figure 5. Parallel Output Switching Characteristics
tRESL
Figure 8. Reset Timing Requirements
REV. A
–7–
ADI [ ADI ]
