AD6620
TIMING DIAGRAMS
CLK, INPUTS, PARALLEL OUTPUTS
SYNC PULSES: SLAVE OR MASTER
RESET with PAR/SER = “1” establishes Parallel Outputs active.
t
CLK
t
CLKH
CLK
t
SY
SYNC NCO
SYNC CIC
SYNC RCF
t
HY
CLK
t
CLKL
Figure 3. CLK Timing Requirements
NOTE:
IN THE SLAVE MODE WITH SINGLE CHANNEL OPERATION, THE WIDTH
OF THE SYNC_NCO SHOULD BE ONE SAMPLE CLOCK CYCLE. IN DUAL
CHANNEL MODE, THE PULSEWIDTH SHOULD BE TWO SAMPLE CLOCK
CYCLES. IF A PULSE LONGER THAN SPECIFIED IS USED, THE NCO WILL
BE INHIBITED AND NOT INCREMENT PROPERLY.
Figure 6. SYNC Slave Timing Requirements
CLK
t
SI
IN[15:0]
EXP[2:0]
A/B
DATA
t
HI
CLK
t
CLK
t
CHP
t
CPL
Figure 4. Input Data Timing Requirements
IN[15:0]
t
CS
t
CH
N
E[2:0]
N+1
t
DPR
t
DPF
t
DPF
A/B
CLK
DV
OUT
VALID OUTPUT DATA
Figure 7. SYNC Master Delay
I/Q
OUT
I
Q
I
Q
OUT[15:0]
I
A
Q
A
I
B
Q
B
RESET
Figure 5. Parallel Output Switching Characteristics
t
RESL
Figure 8. Reset Timing Requirements
REV. A
–7–
AD [ ANALOG DEVICES ]
