AD6600
tENCH
tENCL
tENC
ENCODE
ENCODE
ENCODE
tCLK2ꢀ2
ENCODE
tCR1
tCLK2ꢀL
tCR2
tCLK2ꢀL
tCLK2ꢀ1
tCLK2ꢀH1
tCF1
tCF2
tCLK2ꢀH2
CLK2ꢀ
CLK2ꢀ2
CLK2ꢀ1
CLK2ꢀ2
CLK2ꢀ1
CLK2ꢀ2
tH_DEN
tS_DEN
tH_DEN
tS_DEN
D [10:0]
RSSI [2:0]
tS_AEN
tH_AEN
tH_AEN
tS_AEN
AB_OUT
Figure 11. Encode Setup-and-Hold Time Characteristics
3
2.6
CLK2ꢀ
8
8.4
D [10:0]
RSSI [2:0]
6.2
6
AB_OUT
Figure 12. Typical Output Rise and Fall Times
20
30
50
ENCODE
40%
18
18
30
20
8
8
CLK2ꢀ
Figure 13. Encode = 20 MSPS, Duty Cycle = 40%
30
20
50
ENCODE
60%
23
23
20
30
8
8
CLK2ꢀ
Figure 14. Encode = 20 MSPS, Duty Cycle = 60%
–14–
REV. 0
ADI [ ADI ]
