AD6600
Table II. Selecting AD6600 Operating Mode
Table V. 16-Bit, Fixed-Point Data Format
Mode
Dual: A/B
Single: A
Single: B
Not Valid
A_SEL
1
1
0
0
B_SEL
1
0
1
0
Output vs. Encode Clock
n
n+1 n+2
n+3
A
A
B
–
B
A
B
–
A
A
B
–
B
A
B
–
RSSI
101
100
011
010
001
000
11-Bit Word
DATA
DATA
DATA
DATA
DATA
DATA
16-Bit Data
Format
DATA× 32
DATA× 16
DATA× 8
DATA× 4
DATA× 2
DATA× 1
Corresponds to a
Shift Right of
5
4
3
2
1
0
A_SEL and B_SEL are not logic inputs and should be tied
directly to ground or analog VCC (5 V analog).
In dual channel mode, the AB_OUT signal indicates which
input is currently available on the digital output. When the
AB_OUT is 1, the digital output is the digitized version of
Channel A. Likewise, when AB_OUT is 0, the Channel B is
available on the digital output (Table III).
Table III. AB_OUT for Dual Channel Operation
When mated with the AD6620, Digital Receive Processor Chip,
the AD6600 floating point data (mantissa + exponent) is automati-
cally converted to 16-bit two’s complement format by the AD6620.
APPLYING THE AD6600
Encoding the AD6600
A_SEL and B_SEL = 1
D[10:0], RSSI[2:0]
AB_OUT
Data Output Stage
Output Data vs. Encode Clock
n
n+1
n+2
n+3
A
1
B
0
A
1
B
0
The output stage provides data in the form of mantissa, D[10:0],
and exponent, RSSI[2:0], where D[10:0] represents the output
of the 11-bit ADC coded as two’s complement, and RSSI[2:0]
represents the gain-range setting coded in offset binary. Table
IV shows the nominal gain-ranges for a nominal 2 V p-p differ-
ential full-scale input. Keep in mind that the actual full-scale
input voltage and power will vary with input frequency.
Table IV. Interpreting the RSSI Bits
The AD6600 encode signal must be a high quality, extremely
low phase noise source to prevent degradation of performance.
Digitizing high frequency signals (IF range 70 MHz–250 MHz)
places a premium on encode clock phase noise. SNR perfor-
mance can easily degrade by 3 dB–4 dB with 70 MHz input
signals when using a high-jitter clock source. At higher IFs (up
to 250 MHz), and with high-jitter clock sources, the higher
slew rates of the input signals reduce performance even further.
See AN-501,
Aperture Uncertainty and ADC System Performance
for complete details.
For optimum performance, the AD6600 must be clocked differ-
entially. The encode signal is usually ac-coupled into the ENC
and
ENC
pins via a transformer or capacitors. These pins are
biased internally and require no additional bias.
Figure 18 shows one preferred method for clocking the AD6600.
The sine source (low jitter) is converted from single-ended to
differential using an RF transformer. The back-to-back Schottky
diodes across the transformer secondary limit clock excursions
into the AD6600 to approximately 0.8 V p-p differential. This
helps prevent the larger voltage swings of the clock from feeding
through to other portions of the AD6600, and limits the noise
presented to the encode inputs. A crystal clock oscillator can
also be used to drive the RF transformer if an appropriate
limiting resistor (typically 100
Ω)
is placed in the series with
the primary.
T1–1T
SINE
SOURCE
100
ENCODE
Differential
Analog Input Voltage
(V p-p)
0.5 < V
IN
0.25 < V
IN
< 0.5
0.125 < V
IN
< 0.25
0.0625 < V
IN
< 0.125
0.03125 < V
IN
< 0.0625
V
IN
< 0.03125
RSSI [2:0]
Decimal
Binary Equiv.
101
100
011
010
001
000
5
4
3
2
1
0
Attenuation
or Gain (dB)
–12
–6
0
+6
+12
+18
The digital processing chip which follows the AD6600 can com-
bine the 11 bits of two’s complement data with the 3 RSSI bits
to form a 16-bit equivalent output word. Table V explains how
the RSSI data can be interpreted when using a PLD or ASIC.
Basically, the circuit performs right shifts of the data depending
on the RSSI word. This can also be performed in software using
the following pseudo code fragment:
r0 = dm (rssi);
r2 = 5;
r0 = r2–r0;
r1 = dm (adc); (11 bits, MSB justified into DSP word)
rshift r1, r0; (arithmetic shift to extend the sign bit)
The result of the shifted data is a 16-bit fixed-point word that
can be used as any normal 16-bit word.
AD6600
ENCODE
5082–2810
DIODES
Figure 18. Transformer-Coupled Sine Source
REV. 0
–17–
AD [ ANALOG DEVICES ]
