TableV. Control Register 2Write Definition
The initiate-safe-transfer Bit 9 will request a data transfer from
the SPI safeload registers to the parameter RAM.The safeload
registers contain address-data pairs, and only those registers
that have been written to since the last transfer operation will be
uploaded.The user may poll for this operation to complete by
reading Bit 0 of Control Register 1.The Safeload Mechanism
section goes into more detail on this feature.
Register Bits
Volume Ramp Speed
1 = 160 ms Full RampTime
0 = 20 ms Full RampTime
Serial Port Output Enable
Serial Port Input Select
Bit 10, the halt program bit, is used to initiate a volume ramp-down
followed by a shutdown of the DSP core.The user may poll for
this operation to complete by reading Bit 1 of Control Register 1.
MCLK Input Select
Bit 11 sets the function of the de-emphasis/auxiliary serial input
pin.When this bit is set to 1, the pin will function as an auxiliary
serial input that is clocked by the input mux’s selected clocks.
When set to 0, this pin enables the 44.1 kHz de-emphasis curve.
Table III. Control Register 1Write Definition
MCLK in Frequency Select
MCLK Out Frequency Select
Register Bits
De-emphasis/Auxiliary Serial Input Pin Select
(1 = Auxiliary Serial Input)
Halt Program (1 = Halt)
Initiate SafeTransfer (1 =Transfer)
Enable DCSOUT Output Pin (1 = Enable)
Soft Mute (1 = Start Mute Sequence)
Soft Power-Down (1 = Power-Down)
De-emphasis Curve Select
11 = MCLK_Out = MCLK_In (Feedthrough)
Control Register 2
TableV documents the contents of Control Register 2. Bits 1 and 0
set the frequency of the MCLKOUT pin. If these bits are set to
00, then the MCLKOUT pin is disabled (default).When set to
01, the MCLKOUT pin is set to 512
f
S, which is the same as
the internal master clock used by the DSP core.When set to 10,
this pin is set to 256
f
S, derived by dividing the internal DSP
clock by 2. In this mode, the output 256 fS clock will be inverted
with respect to the input 256 fS clock
.
T
his is not the case with the
feedthrough mode.When set to 11, the MCLKOUT pin mirrors
the selected MCLK input pin (it’s the output of the MCLK mux
selector). Note that the internal DSP master clock may either be
the same as the selected MCLK pin (when MCLK frequency
select is set to 512
f
S mode) or may be derived from the MCLK pin using an internal clock doubler (when MCLK frequency
select is set to 256
f
S). 01 = Right-Justified
11 = Left-Justified
Word Length
Table IV. Control Register 1 Read Definition
Register Bits
Bit 2 selects one of two possible MCLK input frequencies.When
set to 0 (default), the MCLK frequency is set to 512
f
S. In this
mode, the internal DSP clock and the external MCLK are at the
same frequency.When set to 1, the MCLK frequency is set to
256
f
S, and an internal clock doubler is used to generate the DSP Core Shutdown Complete
1 = Shutdown Complete
Safe Memory Load Complete
1 = Complete (Note: Cleared after Read)
0 = Not Complete
Bits 5 and 4 select one of three clock input sources using an inter-
nal mux.To avoid click and pop noises when switching MCLK
sources, it is recommended that the user put the DSP core in
shutdown before switching MCLK sources.
Bit 0 is asserted when all requested safeload registers have been
transferred to the parameter RAM. It is cleared after the read
operation is complete.
Bit 1 is asserted after the requested shutdown of the DSP is com-
pleted.When this bit is set, the user is free to write or read any
RAM location without causing an audio pop or click.
Bits 7 and 6 select one of three serial input sources using an
internal mux. Each source selection includes a separate SDATA,
LRCLK, and BCLK input.To avoid click and pop noises when
switching serial sources, it is recommended that the user put the
DSP core in shutdown before writing to these bits.
REV. A
ADI [ ADI ]
