Table II. SPI Port Address Decoding
Read/WriteWord Length
Register Name
SPI Control Register 1
SPI Control Register 2
Volume Right
Data Capture (SPI Out) #1
Data Capture (SPI Out) #2
Data Capture (Serial Out) Left
Data Capture (Serial Out) Right
Parameter RAM Safe Load Register 0
Parameter RAM Safe Load Register 1
Parameter RAM Safe Load Register 2
Parameter RAM Safe Load Register 3
Parameter RAM Safe Load Register 4
Write: 9-Bit Program CounterValue, 2-Bit Register Address
Write: 9-Bit Program CounterValue, 2-Bit Register Address
Write: 9-Bit Program CounterValue, 2-Bit Register Address
Write: 9-Bit Program CounterValue, 2-Bit Register Address
Write: 8-Bit Parameter RAM Address, 22-Bit Parameter Data
Write: 8-Bit Parameter RAM Address, 22-Bit Parameter Data
Write: 8-Bit Parameter RAM Address, 22-Bit Parameter Data
Write: 8-Bit Parameter RAM Address, 22-Bit Parameter Data
Write: 8-Bit Parameter RAM Address, 22-Bit Parameter Data
Test Register
Program RAM
SPI Address Decoding
Bits 3:2 select one of four serial modes, which are discussed in
the Serial Data Input Port section.
Table II shows the address decoding used in the SPI port.The
SPI address space encompasses a set a registers and two RAMs,
one for holding signal processing parameters and one for hold-
ing the program instructions. Both of the RAMs are loaded on
power-up from on-board boot ROMs.
The de-emphasis curve selection Bits 5:4 turn on the internal
de-emphasis filter for one of three possible sample rates.
Bit 6, the soft power-down bit, stops the internal clocks to the DSP
core, but does not reset the part.The digital power consumption
is reduced to a low level when this bit is asserted. Reset can only
be asserted using the external reset pin.
Control Register 1
Control Register 1 is an 11-bit register that controls data capture,
serial modes, de-emphasis, mute, power-down, and SPI-to-
memory transfers.Table III documents the contents of this register.
Table IV details the two bits in the register’s read operation.
Soft mute (Bit 7) is used to initiate a volume ramp-down sequence.
If the initial volume was set to 1.0, this operation will take 512
audio frames to complete.When this bit is de-asserted, a ramp-up
sequence is initiated until the volume returns to its original setting.
Bits 1:0 set the word length, which is used in right-justified serial
modes to determine where the MSB is located relative to the start
When set, Bit 8 enables the DCSOUT pin.This must be set in
order to read from the data capture serial out registers.
REV. A
ADI [ ADI ]
