AD1857/AD1858
Control Signals
The MODE and DEEMP control inputs are normally connected
HI or LO to establish the operating state of the AD1857/AD1858.
They can be changed dynamically (and asynchronously to the
LRCLK and the master clock) as long as they are stable before
the first serial data input bit (i.e., the MSB) is presented to the
AD1857/AD1858.
APPLICATION ISSUES
Interface to MPEG Audio Decoders
Figure 18 shows the suggested interface to the Philips SAA2500*
MPEG audio decoder IC. The SAA2500 supports 18 bits of
data using an I
2
S-compatible output format.
SCK
19 BCLK
18 LRCLK
20 SDATA
HI
HI
3
6
1
256 x Fs
MODE
384/256
MCLK
SAA2500
WS
SD
FSCLKIN
AD1857
Figure 15 shows the suggested interface to the Analog Devices
ADSP-21xx family of DSP chips, for which several MPEG
audio decode algorithms are available. The ADSP-21xx
supports 16 bits of data using a left-justified DSP serial port
style format.
SCLK
RFS
NC
19 BCLK
18 LRCLK
20 SDATA
HI
NC
HI
3 MODE
6 384/256
1
MCLK
Figure 18. Interface to SAA2500
Figure 19 shows the suggested interface to the Zoran ZR38000*
DSP chip, which can act as an MPEG audio or AC-3 audio
decoder. The ZR38000 supports 16 bits of data using a left-
justified output format.
SCKB
WSB
19 BCLK
18 LRCLK
20 SDATA
LO
HI
3
MODE
ADSP-21xx
TFS
DT
DR
AD1858
ZR38000
SDB
SCKIN
NC = NO CONNECT
AD1857
Figure 15. Interface to ADSP-21xx
6 384/256
1
MCLK
Figure 16 shows the suggested interface to the Texas Instruments
TMS320AV110* MPEG audio decoder IC. The TMS320AV110
supports 18 bits of data using a right-justified output format.
SCLK
19 BCLK
18 LRCLK
20 SDATA
HI
HI
3
6
1
256 x Fs
MODE
384/256
MCLK
256 x Fs
Figure 19. Interface to ZR38000
TMS320AV110
LRCLK
PCMDATA
PCMCLK
Figure 20 shows the suggested interface to the C-Cube
Microsystems CL480* MPEG system decoder IC. The CL480
supports 16 bits of data using a right-justified output format.
AD1858
DA-BCK
19 BCLK
18 LRCLK
20 SDATA
HI
HI
3
6
1
256 x Fs
MODE
384/256
MCLK
DA-LRCK
DA-DATA
DA-XCK
CL480
AD1858
Figure 16. Interface to TMS320AV110
Figure 17 shows the suggested interface to the LSI Logic
L64111* MPEG audio decoder IC. The L64111 supports 16
bits of data using a left-justified output format.
Figure 20. Interface to CL480
SCLKO
LRCLKO
19 BCLK
18 LRCLK
20 SDATA
LO
LO
3
6
1
384 x Fs
MODE
384/256
MCLK
L64111
SERO
SYSCLK
AD1857
Figure 17. Interface to L64111
*All trademarks are properties of their respective holders.
–12–
REV. 0
AD [ ANALOG DEVICES ]
