AD1857/AD1858
OPERATING FEATURES
Serial Data Input Port
Serial Input Port Modes
The AD1857/AD1858 use the frequency of the left/right and
master input clocks to determine the input sample rate. Gen-
erally, the master clock (MCLK) is divided down to synthesize
the left/right clock (LRCLK). LRCLK must run continuously
and transition twice per stereo sample period (except in the left-
justified DSP serial port style mode, when it transitions four
times per stereo sample period). The bit clock (BCLK) is edge-
sensitive and may be used in a gated or burst mode, i.e., a
stream of pulses during data transmission followed by periods of
inactivity. The bit clock is only used to write the audio data
into the serial input port. It is important that the left/right clock
is “clean,” with monotonic rising and falling edge transitions
and no excessive overshoot or undershoot that could cause false
clock triggering of the AD1857/AD1858.
The AD1857/AD1858’s flexible serial data input port accepts
data in twos-complement, MSB first format. The left channel
data field always precedes the right channel data field. The
input data consists of 16, 18 or 20 bits (16 bits only to the
AD1858). All digital inputs are specified to TTL logic levels.
The input data port is configured by a control pin, MODE,
Pin 3. The AD1857 and the AD1858 are identical except for
the serial data input port modes offered. The AD1857 offers
I
2
S-justified and left-justified modes, for 16-, 18- or 20-bit data
words. The AD1858 offers right-justified and DSP serial port
style mode for 16-bit data words.
Note: During the first 30,000 MCLK cycles after coming out of
reset, the AD1857/AD1858 synchronizes its internal sequencer
counter to the incoming LRCLK. After this period of time, it is
assumed that the LRCLK and the internal AD1857/AD1858
output channels could be switched (L to
R
and
R
to L). Therefore,
if the incoming LRCLK is stopped and then restarted with a
different phase, the AD1857/AD1858 should be reset again to
synchronize with this new clock.
LRCLK
INPUT
BCLK
INPUT
SDATA
INPUT
MSB
MSB-1
MSB-2
LSB+2 LSB+1
LSB
The AD1857/AD1858 use an input pin to control the mode
configuration of the input data port. MODE (Pin 3) programs
the input data port mode as follows:
Figure 9 shows the AD1857 left-justified mode. LRCLK is HI
for the left channel, and LO for the right channel. Data is valid
on the rising edge of BCLK. The MSB is left-justified to an
LRCLK transition, with no MSB delay. The left-justified mode
can be used in the 16-, 18- or 20-bit input mode.
MODE (Pin 3)
AD1857 Serial Input Port Mode
LO
HI
Left-Justified (See Figure 9)
I
2
S-Justified (See Figure 10)
MODE (Pin 3)
AD1858 Serial Input Port Mode
LO
HI
Right-Justified (See Figure 11)
Left-Justified DSP Serial Port Style
(See Figure 12)
Figure 10 shows the AD1857 I
2
S-justified mode. LRCLK is
LO for the left channel, and HI for the right channel. Data is
valid on the rising edge of BCLK. The MSB is left-justified to
an LRCLK transition, but with a single BCLK period delay.
The I
2
S-justified mode can be used in the 16-, 18- or 20-bit
input mode.
Figure 11 shows the AD1858 the right-justified mode. LRCLK
is HI for the left channel, and LO for the right channel. Data is
valid on the rising edge of BCLK. The MSB is delayed 16-bit
clock periods from an LRCLK transition so that when there are
64 BCLK periods per LRCLK period, the LSB of the data will
be right-justified to the next LRCLK transition.
LEFT CHANNEL
RIGHT CHANNEL
MSB
MSB-1
MSB-2
LSB+2 LSB+1
LSB
MSB
MSB-1
Figure 9. AD1857 Left-Justified Mode
LRCLK
INPUT
BCLK
INPUT
SDATA
INPUT
MSB
MSB-1
MSB-2
LSB+2 LSB+1
LSB
MSB
MSB-1
MSB-2
LSB+2 LSB+1
LSB
MSB
LEFT CHANNEL
RIGHT CHANNEL
Figure 10. AD1857 I
2
S-Justified Mode
LRCLK
INPUT
BCLK
INPUT
SDATA
INPUT
LSB
MSB
MSB-1 MSB-2
LSB+2 LSB+1
LSB
MSB
MSB-1 MSB-2
LSB+2 LSB+1
LSB
LEFT CHANNEL
RIGHT CHANNEL
Figure 11. AD1858 Right-Justified Mode
–10–
REV. 0
AD [ ANALOG DEVICES ]
