AD1847
tRPWL
RESET
PWRDOWN
SCLK
SDFS
Figure 30. Reset and Power Down Tim ing Diagram
tS
tPD1
tH
TIME
TIME
TIME
SLOT 0
SLOT 1
SLOT 2
BIT 15
BIT 0
tHZ
BIT 0
BIT 14
tDV
SDI
SCLK
SDO
BIT 14
BIT 15
SDFS
SDI/
Figure 28. Tim e Slot Tim ing Diagram
LEFT
RIGHT
CONTROL
STATUS
PLAYBACK
PLAYBACK
16-BIT
STEREO
LEFT
CAPTURE
RIGHT
PLAYBACK
SCLK
SDFS
SDO
LEFT
CONTROL
STATUS
SDI/
PLAYBACK
16-BIT
MONO
LEFT
CAPTURE
LEFT
CAPTURE
SDO
t
PD1
SDI or
SDO
15 14 13
3 2 1 0 15 14 13
LEFT
PB
RIGHT
PB
CONTROL
STATUS
SDI/
8-BIT
STEREO
LEFT
0
RIGHT
0
SDO
CAP
CAP
LAST VALID TIME SLOT
TSO
LEFT
PB
CONTROL
STATUS
SDI/
8-BIT
MONO
t
PD2
LEFT
0
LEFT
0
SDO
CAP
CAP
Figure 29. TSO Tim ing Diagram
Figure 31. Serial Data Form at, 2-Wire System (TSSEL = 1)
TIME
TIME
TIME
TIME
TIME
TIME
SLOT 0
SLOT 1
SLOT 2
SLOT 3
SLOT 4
SLOT 5
SCLK
SDFS
16-BIT
STEREO
SDI/
SDO
CONTROL
CONTROL
CONTROL
LEFT
LEFT
RIGHT
STATUS
STATUS
STATUS
LEFT
LEFT
RIGHT
LEFT
SDI/
16-BIT
SDO MONO
SDI/
SDO STEREO
8-BIT
LEFT
LEFT
0
0
RIGHT
RIGHT
0
0
8-BIT
MONO
SDI/
SDO
CONTROL
STATUS
LEFT
LEFT
LEFT
CAPTURE
PLAYBACK
Figure 32. Serial Data Form at, 1-Wire System (TSSEL = 0)
REV. B
–27–
ADI [ ADI ]
