AD1847
CONTROL REGISTERS
Control Register Mapping
The AD1847 has six 16-bit and thirteen 8-bit on-chip user-
accessible control registers. Control information is sent to the
AD1847 in the 16-bit Control Word. Status information is sent
from the AD1847 in the 16-bit Status Word. Playback Data and
Capture Data each have two 16-bit registers for the right and
left channels. Additional 8-bit Index Registers are accessed via
indirect addressing in the AD1847 Control Word. [Index Regis-
ters are reached with indirect addressing.] The contents of an
indirect addressed Index Register may be readback by the host
CPU or DSP (during the Status Word/Index Readback time
slot) by setting the Read Request (RREQ) bit in the Control
Word. Note that each 16-bit register is assigned its own time
slot, so that the AD1847 always consumes six 16-bit time slots.
Figure 4 shows the mapping of the Control Word, Status Word/
Index Readback and Data registers to time slots when TSSEL = 0.
TSSEL = 0 is used when the SDI and SDO pins are tied to-
gether (i.e., “1-wire” system). This configuration is efficient in
terms of component interconnect (one bidirectional wire for se-
rial data input and output), but inefficient in terms of time slot
usage (six slots consumed on single bidirectional Time Division
Multiplexed [TDM] serial bus). When TSSEL = 0, serial data
input to the AD1847 occurs sequentially with serial data output
from the AD1847 (i.e., Control Word, Left Playback and Right
Playback data is received on the SDI pin, then the Status Word/
lndex Readback, Left Capture and Right Capture data is trans-
mitted on the SDO pin).
Slot
0
1
2
3
4
5
Register Name (16-Bit)
Control Word Input
Left Playback Data Input
Right Playback Data Input
Status Word/Index Readback Output
Left Capture Data Output
Right Capture Data Output
Figure 5 shows the mapping of the Control Word, Status Word/
Index Readback and Data registers to time slots when TSSEL =
1. Note that the six 16-bit registers “share” three time slots.
TSSEL = 1 is used when the SDI and SDO pins are indepen-
dent inputs and output (i.e., “2-wire” system). This configura-
tion is inefficient in terms of component interconnect (two
unidirectional wires for serial data input and output), but effi-
cient in terms of time slot usage (three slots consumed on each
of two unidirectional TDM serial buses). When TSSEL = 1, se-
rial data input to the AD1847 occurs concurrently with serial
data output from the AD1847 (i.e., Control Word reception on
the SDI pin occurs simultaneously with Status Word/lndex
Readback transmission on the SDO pin).
Slot
0
1
2
0
1
2
Register Name (16-Bit)
Control Word Input
Left Playback Data Input
Right Playback Data Input
Status Word/Index Readback Output
Left Capture Data Output
Right Capture Data Output
Figure 5. Control Register Mapping with TSSEL = 1
Figure 4. Control Register Mapping with TSSEL = 0
An Index Register readback request to an invalid index address
(11, 14 and 15) will return the contents of the Status Word. At-
tempts to write to an invalid index address (11, 14 and 15) will
have no effect on the AD1847. As mentioned above, the RREQ
bit of the Control Word is used to request Status Word output
or Index Register readback output during either time slot 3
(TSSEL = 0) or time slot 0 (TSSEL = 1). RREQ is set for In-
dex Register readback output, and reset for Status Word output.
When Index Register readback is requested, the Index Readback
bit format is the same as the Control Word bit format. All status
bits are updated by the AD1847 before a new Control Word is
received (i.e., at frame boundaries). Thus, if TSSEL = 0 and
the Control Word written at slot 0 causes some status bits to
change, the change will show up in the Status Word transmitted
at slot 3 of the same sample.
REV. B
–9–
AD [ ANALOG DEVICES ]
