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7013 参数 Datasheet PDF下载

7013图片预览
型号: 7013
PDF下载: 下载PDF文件 查看货源
内容描述: CMOS TIA IS- 54基带接收端口 [CMOS TIA IS-54 Baseband Receive Port]
分类和应用:
文件页数/大小: 20 页 / 593 K
品牌: ADI [ ADI ]
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(VAA = VDD = +5 V ± 10%; AGND = DGND = 0 V; fMCLK = 6.2208 MHz;  
TA = TMIN to TMAX, unless otherwise noted)  
AD7013–SPECIFICATIONS1  
Parameter  
AD7013A  
Units  
Test Conditions/Comments  
RECEIVE SECTION  
ADC SPECIFICATION  
Number of Input Channels  
4
(IRx–IRx) and  
QRx–QRx); CR12 = 0  
(AUX IRx–AUX IRx) and  
(AUX QRx–AUX QRx); CR12 = 1  
Number of ADC Channels  
Resolution  
2
15  
Bits  
ADC Signal Range  
Differential Signal Range  
2.6  
VBIAS ± 0.65  
Volts p-p  
Volts  
Measured Using an Input Sine Wave of 3 kHz  
For Both Noninverting and  
Inverting Analog Inputs  
Single-Ended Signal Range  
VBIAS  
VBIAS ± 1.3  
Volts  
For Noninverting Analog Inputs;  
Inverting Analog Inputs = VBIAS  
Differential  
0.65 to (VAA–0.65)  
1.3 to (VAA–1.3)  
±7.5  
Volts min/max  
Volts min/max  
%
Single-Ended  
Input Range Accuracy  
Accuracy  
Bias Offset Error  
±7.5  
±55  
mV  
mV  
Autocalibration; VBIAS = min/max  
User Calibration; I & Q Offset  
Adjust Registers Equal to Zero  
Dynamic Specifications  
CMRR  
–40  
dB typ  
Measured Using an Input Sine Wave of  
3 kHz with Both Noninverting and  
Inverting Inputs Tied Together  
Digital Mode Filter; CR11 = 0  
Analog Mode Filter; CR11 = 1  
Digital Mode Filter; CR11 = 0  
Dynamic Range  
SNR2  
70  
65  
65  
68  
60  
63  
dB typ  
dB typ  
dB min  
dB typ  
dB min  
dB typ  
MHz  
Analog Mode Filter; CR11 = 1  
Input Sampling Rate  
Output Word Rate  
1.5552/1.28  
97.2/80  
MCLK = 6.2208 MHz/5.12 MHz; MCLK/4  
MCLK = 6.2208 MHz/5.12 MHz;  
kHz  
4 × Sampling of the Symbol Rate, MCLK/64  
MCLK = 6.2208 MHz/5.12 MHz;  
48.6/40  
kHz  
2 × Sampling of the Symbol Rate, MCLK/128  
RECEIVE DIGITAL FILTERS  
Digital Mode  
MCLK = 6.2208 MHz  
Root-Raised-Cosine  
Settling Time  
Absolute Group Delay  
Frequency Response  
0–7.8975 kHz  
11.9 kHz  
α = 0.35  
329.2  
164.6  
µs  
µs  
±0.05  
–3.0  
–19  
dB max  
dB  
dB  
16.4025 kHz  
> 30 kHz  
–66  
dB max  
Analog Mode  
MCLK = 5.12 MHz  
Brick Wall Filter  
Settling Time  
Absolute Group Delay  
Frequency Response  
0–8 kHz  
400  
200  
µs  
µs  
0 to –0.5  
–3.0  
dB max  
dB  
11.4 kHz  
15 kHz  
–24  
dB  
>17 kHz  
–68  
dB max  
TIA IS-54 RECEIVE SPECIFICATIONS  
Error Vector Magnitude3  
2
1
% rms typ  
% rms typ  
Measured Using a Full-Scale Input  
Error Offset Magnitude3  
–2–  
REV. A