AD7013
(VAA = +5 V ± 10%; VDD = +5 V ± 10%; AGND = DGND =0 V,
fMCLK = 6.2208 MHz; TA = TMIN to TMAX, unless otherwise noted)
CONTROL SERIAL INTERFACE TIMING1
Limit at
Parameter
TA = –40°C to +85°C
Units
Description
t1
t2
t3
t4
160
65
65
20
60
2t1
t1–20
t1–20
25
10
16t5
25
ns min
ns min
ns min
ns min
ns max
ns
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns max
MCLK Cycle Time
MCLK High Time
MCLK Low Time
MCLK Rising Edge to DxCLK Rising Edge Propagation Delay
t5
t6
t7
t8
DxCLK Cycle Time
DxCLK Minimum High Time
DxCLK Minimum Low Time
DxCLK Rising Edge to FRAME IN Setup Time
DxCLK Rising Edge to FRAME IN Hold Time
FRAME IN Cycle Time
DxCLK Rising Edge to DATA IN Setup Time
DxCLK Rising Edge to DATA IN Hold Time
FRAME IN Rising Edge to FRAME OUT Rising Edge Propagation Delay
t9
t10
t11
t12
t13
10
0
25
25
t14
t15
MODE1 Low to FRAME OUT 3-STATE
MODE1 High to FRAME OUT Active
25
NOTE
1t14 is derived from the measured time taken by the FRAME OUT pin to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove the effects of charging or discharging the 80 pF capacitor. This means that the time quoted in the Timing Characteristics is the
I
1.6mA
OL
+2.1V
TO OUTPUT PIN
C
L
50pF
I
OH
200µA
Figure 1. Load Circuit for Digital Outputs
t2
t1
t3
MxCLK (I)
DxCLK (O)
t4
t6
t5
t7
t9
t8
t10
FRAME IN (I)
DATA IN (I)
t12
t11
DB9
DB8
DB1
DB0
A3
A0
S1
S0
DATA
ADDRESS
IGNORED
t13
t14
t15
FRAME OUT (O)
MODE1 (I)
3 – STATE
NOTE: (O) INDICATES AN OUTPUT, (I) INDICATES AN INPUT, MODE1 = LOGIC HIGH
Figure 2. 16-Bit Serial Interface for Writing to the AD7013 Internal Registers
–6–
REV. A
ADI [ ADI ]
