AD14060/AD14060L
D ETAILED D ESCRIP TIO N
Ar chitectur al Featur es
ADSP-21060 Cor e
T he SHARCs contain 4 Mbits of on-chip SRAM each, orga-
nized as two blocks of 2 Mbits, which can be configured for
different combinations of code and data storage. T he memory
can be configured as a maximum of 128K words of 32-bit data,
256K words of 16-bit data, 80K words of 48-bit instructions (or
40-bit data), or combinations of different word sizes up to
4 megabits. A 16-bit floating-point storage format is supported
which effectively doubles the amount of data that may be stored
on chip. Conversion between the 32-bit floating point and 16-
bit floating point formats is done in a single instruction. Each
memory block is dual-ported for single-cycle, independent
accesses by the core processor and I/O processor or DMA con-
troller. T he dual-ported memory and separate on-chip buses
allow two data transfers from the core and one from I/O, all in a
single cycle.
The AD14060/AD14060L is based on the powerful ADSP-21060
(SHARC) DSP chip. T he ADSP-21060 SHARC combines a
high performance floating-point DSP core with integrated, on-
chip system features including a 4 Mbit SRAM memory, host
processor interface, DMA controller, serial ports, and both link
port and parallel bus connectivity for glueless DSP multiprocess-
ing, (see Figure 1). It is fabricated in a high speed, low power
CMOS process, and has a 25 ns instruction cycle time. The arith-
metic/ logic unit (ALU), multiplier and shifter all perform single-
cycle instructions, and the three units are arranged in parallel,
maximizing computational throughput.
T he SHARC features an enhanced Harvard architecture in
which the data memory (DM) bus transfers data, and the pro-
gram memory (PM) bus transfers both instructions and data.
T here is also an on-chip instruction cache which selectively
caches only those instructions whose fetches conflict with the
PM bus data accesses. T his combines with the separate program
and data memory buses to enable three-bus operation for fetch-
ing an instruction and two operands, all in a single cycle. T he
SHARC also contains a general purpose data register file, which
is a 10-port, 32-register (16 primary, 16 secondary) file. Each
SHARC’s core also implements two data address generators
(DAGs), implementing circular data buffers in hardware. T he
DAGs contain sufficient registers to allow the creation of up to
32 circular buffers. T he 48-bit instruction word accommodates a
variety of parallel operations, for concise programming. For ex-
ample, the ADSP-21060 can conditionally execute a multiply, an
add, a subtract, and a branch, all in a single instruction.
Shar ed Mem or y Multipr ocessing
T he AD14060/AD14060L takes advantage of the powerful
multiprocessing features built into the SHARC. The SHARCs are
connected to maximize the performance of this cluster-of-four
architecture, and still allow for off-module expansion. T he
AD14060/AD14060L in itself is a complete shared memory
multiprocessing system, as shown in Figure 3. T he unified ad-
dress space of the SHARCs allows direct interprocessor ac-
cesses of each SH ARCs’ internal memory. In other words, each
SHARC can directly access the internal memory and IOP registers
of each of the other SHARCs by simply reading or writing to the
appropriate address in multiprocessor memory space (see Figure
2)—this is called a direct read or direct write.
DUAL-PORTED SRAM
CORE PROCESSOR
INSTRUCTION
TIMER
JTAG
TWO INDEPENDENT
DUAL-PORTED BLOCKS
7
CACHE
32 x 48-BIT
TEST AND
EMULATION
PROCESSOR PORT
ADDR DATA
I/O PORT
DATA ADDR
DATA
ADDR
ADDR
DATA
DAG1
8 x 4 x 32
DAG2
8 x 4 x 24
PROGRAM
SEQUENCER
EXTERNAL
PORT
IOD
48
IOA
17
PM ADDRESS BUS
24
32
32
48
ADDR BUS
MUX
DM ADDRESS BUS
PM DATA BUS
MULTIPROCESSOR
INTERFACE
48
BUS
CONNECT
(PX)
DATA BUS
MUX
DM DATA BUS 40/32
HOST PORT
4
6
DMA
DATA
REGISTER
FILE
IOP
REGISTERS
MEMORY MAPPED)
CONTROLLER
(
SERIAL PORTS
(2)
16 x 40-BIT
BARREL
SHIFTER
6
MULTIPLIER
ALU
CONTROL,
STATUS, AND
DATA BUFFERS
36
LINK PORTS
(6)
I/O PROCESSOR
Figure 1. ADSP-21060 Processor Block Diagram (Core of the AD14060)
REV. A
–2–
ADI [ ADI ]
