AD14060/AD14060L
P IN FUNCTIO N D ESCRIP TIO NS
T CLKx, RCLKx, LxDAT3-0, LxCLK, LxACK, T MS and
T DI)—these pins can be left floating. T hese pins have a logic-
level hold circuit that prevents the input from floating internally.
AD14060/AD14060L pin definitions are listed below. Inputs
identified as synchronous (S) must meet timing requirements
with respect to CLKIN (or with respect to T CK for T MS,
T DI). Inputs identified as asynchronous (A) can be asserted
asynchronously to CLKIN (or to T CK for TRST).
I = Input
P = Power Supply (A/D) = Active Drive
O = Output
G = Ground
S = Synchronous
A = Asynchronous
(O/D) = Open Drain
Unused inputs should be tied or pulled to VDD or GND, except
for ADDR31-0, DAT A47-0, FLAG2-0, SW, and inputs that have
internal pull-up or pull-down resistors (CPA, ACK, DT x, DRx,
T = Three-State (when SBTS is asserted, or when the AD14060/
AD14060L is a bus slave)
P in
Type
Function
ADDR31-0
I/O/T
Exter nal Bus Addr ess. (Common to all SHARCs) T he AD14060/AD14060L outputs addresses for
external memory and peripherals on these pins. In a multiprocessor system, the bus master outputs
addresses for read/writes on the internal memory or IOP registers of slave ADSP-2106xs. The AD14060/
AD14060L inputs addresses when a host processor or multiprocessing bus master is reading or writing
the internal memory or IOP registers of internal ADSP-21060s.
DAT A47-0
I/O/T
O/T
Exter nal Bus D ata. (Common to all SHARCs) T he AD14060/AD14060L inputs and outputs data and
instructions on these pins. 32-bit single-precision floating-point data and 32-bit fixed-point data is trans-
ferred over bits 47-16 of the bus. 40-bit extended-precision floating-point data is transferred over bits 47-
8 of the bus. 16-bit short word data is transferred over bits 31-16 of the bus. In PROM boot mode, 8-bit
data is transferred over bits 23-16. Pull-up resistors on unused DAT A pins are not necessary.
MS3-0
Mem or y Select Lines. (Common to all SHARCs) T hese lines are asserted (low) as chip selects for the
corresponding banks of external memory. Memory bank size must be defined in the individual ADSP-
21060’s system control registers (SYSCON). T he MS3-0 lines are decoded memory address lines that
change at the same time as the other address lines. When no external memory access is occurring the MS3-0
lines are inactive; they are active, however, when a conditional memory access instruction is executed, whether
or not the condition is true. MS0 can be used with the PAGE signal to implement a bank of DRAM memory
(Bank 0). In a multiprocessing system, the MS3-0 lines are output by the bus master.
RD
I/O/T
I/O/T
O/T
Mem or y Read Str obe. (Common to all SH ARCs) T his pin is asserted (low) when the AD14060/
AD14060L reads from external devices or when the internal memory of internal ADSP-2106xs is being
accessed. External devices (including other ADSP-2106xs) must assert RD to read from the AD14060/
AD14060L’s internal memory. In a multiprocessing system, RD is output by the bus master and is input
by all other ADSP-2106xs.
WR
Mem or y Wr ite Str obe. (Common to all SH ARCs) T his pin is asserted (low) when the AD14060/
AD14060L writes to external devices or when the internal memory of internal ADSP-2106xs is being ac-
cessed. External devices (including other ADSP-2106xs) must assert WR to write to the AD14060/
AD14060L’s internal memory. In a multiprocessing system WR is output by the bus master and is input by
all other ADSP-2106xs.
PAGE
D RAM P age Boundar y. (Common to all SHARCs) T he AD14060/AD14060L asserts this pin to signal
that an external DRAM page boundary has been crossed. DRAM page size must be defined in the indi-
vidual ADSP-21060’s memory control register (WAIT ). DRAM can only be implemented in external
memory Bank 0; the PAGE signal can only be activated for Bank 0 accesses. In a multiprocessing system,
PAGE is output by the bus master.
ADRCLK
O/T
Clock O utput Refer ence. (Common to all SHARCs) In a multiprocessing system, ADRCLK is output
by the bus master.
SW
I/O/T
Synchr onous Wr ite Select. (Common to all SHARCs) T his signal is used to interface the AD14060/
AD14060L to synchronous memory devices (including other ADSP-2106xs). T he AD14060/AD14060L
asserts SW (low) to provide an early indication of an impending write cycle, which can be aborted if WR
is not later asserted (e.g., in a conditional write instruction). In a multiprocessing system, SW is output
by the bus master and is input by all other ADSP-2106xs to determine if the multiprocessor memory
access is a read or write. SW is asserted at the same time as the address output. A host processor using
synchronous writes must assert this pin when writing to the AD14060/AD14060L.
ACK
I/O/S
Mem or y Acknowledge. (Common to all SHARCs) External devices can deassert ACK (low) to add
wait states to an external memory access. ACK is used by I/O devices, memory controllers, or other pe-
ripherals to hold off completion of an external memory access. T he AD14060/AD14060L deasserts
ACK, as an output, to add wait states to a synchronous access of its internal memory. In a multiprocess-
ing system, a slave ADSP-2106x deasserts the bus master’s ACK input to add wait state(s) to an access
of its internal memory. T he bus master has a keeper latch on its ACK pin that maintains the input at the
level it was last driven to.
REV. A
–8–
ADI [ ADI ]
