a
PERFORMANCE FEATURES
ADSP-21060 Core Processor (.
. .
4)
480 MFLOPS Peak, 320 MFLOPS Sustained
25 ns Instruction Rate, Single-Cycle
Instruction Execution–Each of Four Processors
16 Mbit Shared SRAM (Internal to SHARCs)
4 Gigawords Addressable Off-Module Memory
Twelve 40 Mbyte/s Link Ports (Three per SHARC)
Four 40 Mbit/s Independent Serial Ports (One from
Each SHARC)
One 40 Mbit/s Common Serial Port
5 V and 3.3 V Operation
32-Bit Single Precision and 40-Bit Extended
Precision IEEE Floating Point Data Formats, or
32-Bit Fixed Point Data Format
IEEE JTAG Standard 1149.1 Test Access Port and
On-Chip Emulation
PACKAGING FEATURES
308-Lead Ceramic Quad Flatpack (CQFP)
2.05" (52 mm) Body Size
Cavity Up or Down, Configurable
Low Profile, 0.160" Height
Hermetic
25 Mil (0.65 mm) Lead Pitch
29 Grams (typical)
JC
= 0.36 C/W
GENERAL DESCRIPTION
CPA
SPORT 1
TDI
Quad-SHARC
DSP Multiprocessor Family
AD14060/AD14060L
FUNCTIONAL BLOCK DIAGRAM
CS
TIMEXP
LINK 1
LINK 3
LINK 4
FLAG
2,0
IRQ
2-0
CS
TIMEXP
LINK 1
LINK 3
LINK 4
LINK 0
LINK 2
LINK 5
TDO
LINK 0
LINK 2
LINK 5
TDI
®
EBOOT,
LBOOT,
BMS
EMU
CLKIN
EBOOT,
LBOOT,
BMS
EMU
CLKIN
(ID
2-0
= 1)
SPORT 0
TCK, TMS, TRST
FLAG
1
(ID
2-0
= 2)
RESET
AD14060/
AD14060L
SHARC BUS (
ADDR
31-0
,
DATA
47-0
,
MS
3-0
,
RD, WR, PAGE, ADRCLK, SW, ACK,
SBTS, HBR, HBG, REDY, BR
6-1
, RPBA, DMAR
1.2
, DMAG
1.2
)
FLAG
3
EBOOT,
LBOOT,
BMS
SPORT 0
TCK, TMS, TRST
FLAG
1
EBOOT,
LBOOT,
BMS
FLAG
3
EMU
CLKIN
CPA
SPORT 1
TDO
SHARC_D
(ID
2-0
= 4)
FLAG
2,0
CS
TIMEXP
LINK 1
LINK 3
LINK 4
IRQ
2-0
The AD14060/AD14060L Quad-SHARC is the first in a family
of high performance DSP multiprocessor modules. The core of
the multiprocessor is the ADSP-21060 DSP microcomputer.
The AD14060/AD14060L modules have the highest perfor-
mance —density and lowest cost—performance ratios of any in
their class. They are ideal for applications requiring higher levels
of performance and/or functionality per unit area.
The AD14060/AD14060L takes advantage of the built-in multi-
processing features of the ADSP-21060 to achieve 480 peak
MFLOPS with a single chip type, in a single package. The on-
chip SRAM of the DSPs provides 16 Mbits of on-module
shared SRAM. The complete shared bus (48 data, 32 address)
is also brought off-module for interfacing with expansion
memory or other peripherals.
The ADSP-21060 link ports are interconnected to provide
direct communication among the four SHARCs as well as high
speed off-module access. Internally, each SHARC has a direct
link port connection. Externally, each SHARC has a total of
120 Mbytes/s link port bandwidth.
Multiprocessor performance is enhanced with embedded power
and ground planes, matched impedance interconnect, and opti-
mized signal routing lengths and separation. The fully tested
and ready-to-insert multiprocessor also significantly reduces
board space.
SHARC is a registered trademark of Analog Devices, Inc.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1997
FLAG
2,0
TIMEXP
LINK 1
LINK 3
LINK 4
IRQ
2-0
CS
LINK 0
LINK 2
LINK 5
TDI
LINK 0
LINK 2
LINK 5
TDO
SHARC_C
(ID
2-0
= 3)
SPORT 0
TCK, TMS, TRST
FLAG
1
FLAG
3
TDI
CPA
SPORT 1
EMU
CLKIN
RESET
RESET
SPORT 0
TCK, TMS, TRST
FLAG
1
FLAG
3
TDO
SHARC_A
SHARC_B
CPA
SPORT 1
RESET
FLAG
2,0
IRQ
2-0
AD [ ANALOG DEVICES ]
