AD14060/AD14060L
P in
Type
Function
SBTS
I/S
Su spen d Bu s T h r ee- State. (Common to all SHARCs) External devices can assert SBTS (low) to
place the external bus address, data, selects, and strobes in a high impedance state for the following cycle.
If the AD14060/AD14060L attempts to access external memory while SBTS is asserted, the processor
will halt and the memory access will not be completed until SBTS is deasserted. SBTS should only be
used to recover from host processor/AD14060/AD14060L deadlock, or used with a DRAM controller.
HBR
HBG
I/A
I/O
H ost Bus Request. (Common to all SHARCs) Must be asserted by a host processor to request control
of the AD14060/AD14060L’s external bus. When HBR is asserted in a multiprocessing system, the
ADSP-2106x that is bus master will relinquish the bus and assert HBG. T o relinquish the bus, the
ADSP-2106x places the address, data, select, and strobe lines in a high impedance state. HBR has priority
over all ADSP-2106x bus requests (BR6-1) in a multiprocessing system.
H ost Bus Gr ant. (Common to all SHARCs) Acknowledges an HBR bus request, indicating that the
host processor may take control of the external bus. HBG is asserted (held low) by the AD14060/AD14060L
until HBR is released. In a multiprocessing system, HBG is output by the ADSP-2106x bus master and is
monitored by all others.
CSA
I/A
I/A
I/A
I/A
O
Chip Select. Asserted by host processor to select SHARC_A.
Chip Select. Asserted by host processor to select SHARC_B.
Chip Select. Asserted by host processor to select SHARC_C.
Chip Select. Asserted by host processor to select SHARC_D.
CSB
CSC
CSD
REDY (O/D)
H ost Bus Acknowledge. (Common to all SHARCs) T he AD14060/AD14060L deasserts REDY (low)
to add wait states to an asynchronous access of its internal memory or IOP registers by a host. Open drain
output (O/D) by default; can be programmed in ADREDY bit of SYSCON register of individual ADSP-
21060s to be active drive (A/D). REDY will only be output if the CS and HBR inputs are asserted.
BR6-1
I/O/S
I/S
Multipr ocessing Bus Requests. (Common to all SHARCs) Used by multiprocessing ADSP-2106xs to
arbitrate for bus mastership. An ADSP-2106x only drives its own BRx line (corresponding to the value of
its ID2-0 inputs) and monitors all others. In a multiprocessor system with less than six ADSP-2106xs, the
unused BRx pins should be pulled high; BR4-1 must not be pulled high or low because they are outputs.
RPBA
Rotating P r ior ity Bus Ar bitr ation Select. (Common to all SHARCs) When RPBA is high, rotating
priority for multiprocessor bus arbitration is selected. When RPBA is low, fixed priority is selected. This
signal is a system configuration selection that must be set to the same value on every ADSP-2106x. If the
value of RPBA is changed during system operation, it must be changed in the same CLKIN cycle on
every ADSP-2106x.
CPAy (O/D)
I/O
Cor e P r ior ity Access. (y = SHARC_A, B, C, D) Asserting its CPA pin allows the core processor of an
ADSP-2106x bus slave to interrupt background DMA transfers and gain access to the external bus.
CPA is an open drain output that is connected to all ADSP-2106x in the system if this function is
required. T he CPA pin of each internal ADSP-21060 is brought out individually. T he CPA pin has
an internal 5 kΩ pull-up resistor. If core access priority is not required in a system, the CPA pin
should be left unconnected.
DT 0
O/T
I
D ata Tr ansm it (Common Serial Ports 0 to all SHARCs, T DM). DT pin has a 50 kΩ internal pull-up
resistor.
DR0
D ata Receive (Common Serial Ports 0 to all SHARCs, T DM). DR pin has a 50 kΩ internal pull-up
resistor.
T CLK0
RCLK0
I/O
I/O
Tr an sm it C lock (Common Serial Ports 0 to all SH ARCs, T DM). T CLK pin has a 50 kΩ internal
pull-up resistor.
Receive Clock (Common Serial Ports 0 to all SHARCs, T DM). RCLK pin has a 50 kΩ internal pull-up
resistor.
T FS0
RFS0
DT y1
I/O
I/O
O/T
Tr ansm it Fr am e Sync (Common Serial Ports 0 to all SHARCs, T DM).
Receive Fr am e Sync (Common Serial Ports 0 to all SHARCs, T DM).
D ata Tr ansm it (Serial Port 1 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D) DT pin
has a 50 kΩ internal pull-up resistor.
DRy1
I
D ata Receive (Serial Port 1 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D) DR pin
has a 50 kΩ internal pull-up resistor.
REV. A
–9–
ADI [ ADI ]
