AD652
THEORY OF OPERATION
A synchronous VFC is similar to other voltage-to-frequency
converters in that an integrator is used to perform a charge-
balance of the input signal with an internal reference current.
However, rather than using a one-shot as the primary timing
element, which requires a high quality and low drift capacitor, a
synchronous voltage-to-frequency converter (SVFC) uses an
external clock. This allows the designer to determine the system
stability and drift based upon the external clock selected. A
crystal oscillator may also be used if desired.
3
2
1
20
19
AD652
SYNCHRONOUS
VOLTAGE-TO-FREQUENCY
CONVERTER
5V
REFERENCE
OP AMP OUT
OP AMP "–"
OP AMP "+"
5V INPUT
4
5
6
7
8
18 COMP "+"
17 COMP "–"
"D"
FLOP
Q
D
16 ANALOG GND
15 DIGITAL GND
14 FREQ OUT
AND
The SVFC architecture provides other system advantages
besides low drift. If the output frequency is measured by
counting pulses gated to a signal that is derived from the clock,
the clock stability is unimportant and the device simply
performs as a voltage-controlled frequency divider, producing a
high resolution A/D. If a large number of inputs must be
monitored simultaneously in a system, the controlled timing
relationship between the frequency output pulses and the user-
supplied clock greatly simplifies this signal acquisition. Also, if
the clock signal is provided by a VFC, the output frequency of
the SVFC is proportional to the product of the two input
voltages. Therefore, multiplication and A-to-D conversion on
two signals are performed simultaneously.
10kΩ
Q
CK
10kΩ
ONE
SHOT
1mA
16kΩ
10V INPUT
4kΩ
9
10
11
12
13
NC = NO CONNECT
Figure 3. PLCC Pin Configuration
Figure 4 shows the typical up-and-down ramp integrator output
of a charge-balance VFC. After the integrator output has
crossed the comparator threshold and the output of the AND
gate has gone high, nothing happens until a negative edge of the
clock comes along to transfer the information to the output of
the D FLOP. At this point, the clock level is low, so the latch does
not change state. When the clock returns high, the latch output
goes high and drives the switch to reset the integrator; at the
same time, the latch drives the AND gate to a low output state.
On the very next negative edge of the clock, the low output state
of the AND gate is transferred to the output of the D FLOP.
When the clock returns high, the latch output goes low and
drives the switch back into the Integrate mode. At the same
time, the latch drives the AND gate to a mode where it
truthfully relays the information presented to it by the
comparator.
AD652
SYNCHRONOUS
VOLTAGE-TO-
5V
+V
1
2
3
4
5
6
7
8
FREQUENCY
CONVERTER
16 COMP REF
15 COMP "+"
S
REFERENCE
TRIM
TRIM
14 COMP "–"
OP AMP OUT
OP AMP "–"
OP AMP "+"
10 VOLT INPUT
13 ANALOG GND
12 DIGITAL GND
11 FREQ OUT
10 CLOCK INPUT
ONE
SHOT
20kΩ
1mA
Q
CK
–V
S
9
C
OS
D
AND
"D"
Q
FLOP
Figure 2. CERDIP Pin Configuration
The pinouts of the AD652 SVFC are shown in Figure 2 and
Figure 3. A block diagram of the device configured as an SVFC,
along with various system waveforms, is shown in Figure 4.
Because the reset pulses applied to the integrator are exactly one
clock period long, the only place where drift can occur is in a
variation of the symmetry of the switching speed with
temperature.
Since each reset pulse is identical, the AD652 SVFC produces a
very linear voltage-to-frequency transfer relation. Also, because
all reset pulses are gated by the clock, there are no problems
with dielectric absorption causing the duration of a reset pulse
to be influenced by the length of time since the last reset.
Rev. C | Page 6 of 28
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