AD652
AD652JP/AQ/SQ
AD652KP/BQ
Parameter
Min
Typ
Max
Min
Typ
Max
Unit
COMPARATOR
Input Bias Current
Common-Mode Voltage
CLOCK INPUT
Maximum Frequency
Threshold Voltage (Referred to Pin ±2)
TMIN to TMAX
0.ꢀ
ꢀ
0.ꢀ
ꢀ
µA
V
−VS + 4
4
+ VS − 4
−VS + 4
4
+VS − 4
ꢀ
±.2
ꢀ
±.2
MHz
V
V
0.8
2.0
0.8
2.0
Input Current
(−VS < VCLK < +VS)
Voltage Range
Rise Time
ꢀ
ꢀ
µA
V
µs
20
+VS
2
20
+VS
2
−VS
−VS
OUTPUT STAGE
VOL (IOUT = ±0 mA)
IOL
V
0.4
0.4
VOL < 0.8 V
mA
mA
µA
ns
ns
pF
15
8
10
250
15
8
10
250
VOL < 0.4 V, TMIN to TMAX
IOH (Off Leakage)
Delay Time, Positive Clock Edge to Output Pulse
Fall Time (Load = ꢀ00 pF and ISINK = ꢀ mA)
Output Capacitance
OUTPUT ONE-SHOT
Pulse Width, tOS
0.0±
200
±00
ꢀ
0.0±
200
±00
ꢀ
150
150
COS = 300 pF
COS = ±000 pF
±.ꢀ
ꢀ
±
4
±.ꢀ
ꢀ
µs
µs
1
4
2
6
2
6
REFERENCE OUTPUT
Voltage
Drift
ꢀ.0
ꢀ.0
V
4.950
5.050
100
4.975
5.025
50
ppm/°C
Output Current
Source TMIN to TMAX
Sink
mA
µA
10
±00
10
±00
ꢀ00
ꢀ00
Power Supply Rejection
Supply Range = ±±2.ꢀ V to ±±7.ꢀ V
Output Impedance (Sourcing Current)
POWER SUPPLY
0.0±ꢀ
2
0.0±ꢀ
2
%/V
Ω
0.3
0.3
Rated Voltage
Operating Range
Dual Supply
Single Supply (−VS = 0)
Quiescent Current
Digital Common
Analog Common
TEMPERATURE RANGE
Specified Performance
JP, KP Grade
±±ꢀ
±±ꢀ
±±±
±±ꢀ
±±ꢀ
±±±
V
±6
+±2
±±8
+36
15
+VS − 4
+VS
±6
+±2
±±8
+36
15
+VS − 4
+VS
V
V
mA
V
V
−VS
−VS
–VS
−VS
0
−40
−ꢀꢀ
+70
+8ꢀ
+±2ꢀ
0
−40
+70
+8ꢀ
°C
°C
°C
AQ, BQ Grade
SQ Grade
± Referred to internal VREF. In PLCC package, tested on ±0 V input range only.
Rev. C | Page 4 of 28
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