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5962-9312601MXA 参数 Datasheet PDF下载

5962-9312601MXA图片预览
型号: 5962-9312601MXA
PDF下载: 下载PDF文件 查看货源
内容描述: [Complete 12-Bit 1.25 MSPS Monolithic A/D Converter]
分类和应用: 信息通信管理转换器
文件页数/大小: 16 页 / 393 K
品牌: ADI [ ADI ]
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AD1671  
Table I is a list of grounding and decoupling rules that should  
be reviewed before laying out a printed circuit board.  
The gain trim is done by applying a signal 1 1/2 LSBs below the  
nominal full scale (4.998 V for a 5 V range). Trim R2 to give  
the last transition (1111 1111 1110 to 1111 1111 1111). This  
circuit will give approximately ±0.5% FS of adjustment range.  
Table I. Grounding and Decoupling Guidelines  
Power Supply  
V
IN  
0 TO +5V  
AIN1  
AIN2  
Decoupling  
Comment  
25  
5k  
5k  
SHA  
+5V  
R1  
Capacitor Values  
0.1 µF (Ceramic) and 1 µF  
(Tantalum) Surface Mount Chip  
Capacitors Recommended to  
Reduce Lead Inductance  
50k  
OFFSET  
10k  
ADJ  
–5V  
R2  
50Ω  
SHA OUT  
GAIN  
ADJ  
AD1671  
Capacitor Locations  
Directly at Positive and Negative  
Supply Pins to Common Ground  
Plane  
BPO/UPO  
REF IN  
REF OUT  
Reference (REF OUT)  
Capacitor Value  
Grounding  
1µF  
1 µF (Tantalum) to ACOM  
Figure 9. Unipolar (0 V to +5 V) Calibration  
Analog Ground  
Ground Plane or Wide Ground  
Return Connected to the Analog  
Power Supply  
BIPOLAR (؎5 V) CALIBRATION  
The connections for the bipolar ±5 V input range is shown in  
Figure 10.  
Reference Ground  
(REF COM)  
Critical Common Connections  
Should be Star Connected to REF  
COM (as Shown in Figure 8)  
V
IN  
AIN1  
25  
5k  
5k  
–5V TO +5V  
SHA  
+5V  
R1  
AIN2  
Digital Ground  
Ground Plane or Wide Ground  
Return Connected to the Digital  
Power Supply  
50k  
OFFSET  
10k  
ADJ  
–5V  
R2  
50Ω  
SHA OUT  
GAIN  
ADJ  
AD1671  
Analog and Digital Ground Connected Together Once at the  
AD1671  
BPO/UPO  
REF IN  
UNIPOLAR (0 V TO +5 V) CALIBRATION  
REF OUT  
The AD1671 is factory trimmed to minimize offset, gain and  
linearity errors. In some applications the offset and gain errors  
of the AD1671 need to be externally adjusted to zero. This is  
accomplished by trimming the voltage at AIN2 (Pin 22). The  
circuit in Figure 9 is recommended for calibrating offset and  
gain errors of the AD1671 when configured in the 0 V to +5 V  
input range. If the offset trim resistor R1 is used, it should be  
trimmed as follows, although a different offset can be set for a  
particular system requirement. This circuit will give approxi-  
mately ±5 mV of offset trim range. Nominally the AD1671 is  
intended to have a 1/2 LSB offset so that the exact analog input  
for a given code will be in the middle of that code (halfway be-  
tween the transitions to the codes above it and below it). Thus,  
the first transition (from 0000 0000 0000 to 0000 0000 0001)  
will occur for an input level of +1/2 LSB (0.61 mV for 5 V  
range).  
1µF  
Figure 10. Bipolar (±5 V) Calibration  
Bipolar calibration is similar to unipolar calibration. First, a sig-  
nal 1/2 LSB above negative full scale (–4.9988 V) is applied and  
R1 is trimmed to give the first transition (0000 0000 0000 to  
0000 0000 0001). Then a signal 1 1/2 LSB below positive full  
scale (+4.9963 V) is applied and R2 is trimmed to give the last  
transition (1111 1111 1110 to 1111 1111 1111).  
REV. B  
–9–