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5962-9312601MXA 参数 Datasheet PDF下载

5962-9312601MXA图片预览
型号: 5962-9312601MXA
PDF下载: 下载PDF文件 查看货源
内容描述: [Complete 12-Bit 1.25 MSPS Monolithic A/D Converter]
分类和应用: 信息通信管理转换器
文件页数/大小: 16 页 / 393 K
品牌: ADI [ ADI ]
 浏览型号5962-9312601MXA的Datasheet PDF文件第4页浏览型号5962-9312601MXA的Datasheet PDF文件第5页浏览型号5962-9312601MXA的Datasheet PDF文件第6页浏览型号5962-9312601MXA的Datasheet PDF文件第7页浏览型号5962-9312601MXA的Datasheet PDF文件第9页浏览型号5962-9312601MXA的Datasheet PDF文件第10页浏览型号5962-9312601MXA的Datasheet PDF文件第11页浏览型号5962-9312601MXA的Datasheet PDF文件第12页  
AD1671  
85  
80  
75  
70  
65  
60  
55  
50  
45  
40  
Figure 4 plots both S/(N+D) and Effective Number of Bits  
(ENOB) for a 100 kHz input signal sampled from 666 kHz to  
1.25 MHz.  
11.75  
11.50  
11.25  
11.00  
72.5  
72  
71.5  
71  
70.5  
70  
–25  
–50 –45 –40 –35 –30  
–20 –15 –10 –5  
0
69.5  
69  
ANALOG INPUT – dB  
68.5  
68  
Figure 7. Spurious Free Dynamic Range vs. Input  
Amplitude, fIN = 250 kHz  
666  
714  
769  
833  
909  
1000  
1111  
1250  
SAMPLING FREQUENCY – kHz  
APPLYING THE AD1671  
GROUNDING AND DECOUPLING RULES  
Figure 4. S/(N/D) vs. Sampling Frequency, fIN = 100 kHz  
Proper grounding and decoupling should be a primary design  
objective in any high speed, high resolution system. The  
AD1671 separates analog and digital grounds to optimize the  
management of analog and digital ground currents in a system.  
The AD1671 is designed to minimize the current flowing from  
REF COM (Pin 20) by directing the majority of the current  
from VCC (+5 V–Pin 28) to VEE (–5 V–Pin 1). Minimizing ana-  
log ground currents hence reduces the potential for large ground  
voltage drops. This can be especially true in systems that do not  
utilize ground planes or wide ground runs. REF COM is also  
configured to be code independent, therefore reducing input de-  
pendent analog ground voltage drops and errors. Code depen-  
dent ground current is diverted to ACOM (Pin 27). Also critical  
in any high speed digital design is the use of proper digital  
grounding techniques to avoid potential CMOS “ground  
bounce.” Figure 3 is provided to assist in the proper layout,  
grounding and decoupling techniques.  
Figure 5 is a THD plot for a full-scale 100 kHz input signal with  
the sample frequency swept from 666 kHz to 1.25 MHz.  
–68  
–70  
–72  
–74  
–76  
–78  
–80  
–82  
–84  
–86  
666  
714  
769  
833  
909  
1000  
1111  
1250  
SAMPLING FREQUENCY – kHz  
Figure 5. THD vs. Sampling Rate, fIN = 100 kHz  
+5V  
–5V  
+5V  
The AD1671’s SFDR performance is ideal for use in communi-  
cation systems such as high speed modems and digital radios.  
The SFDR is better than 84 dB with sample rates up to 1.11 MHz  
and increases as the input signal amplitude is attenuated by ap-  
proximately 3 dB. Note also the SFDR is typically better than  
80 dB with input signals attenuated by up to –7 dB.  
0.1µF  
0.1µF 10µF  
0.1µF 10µF  
10µF  
28  
1
18  
V
V
V
LOGIC  
CC  
EE  
23  
22  
20  
27  
BIT 1 13  
AIN1  
–68  
–70  
–72  
AD1671  
V
(±5V)  
2
BIT 12  
AIN2  
IN  
REF COM  
–74  
–76  
–78  
–80  
–82  
–84  
–86  
–88  
–90  
ACOM  
AGP*  
ENCODE 17  
19  
25  
DCOM  
DGP*  
16  
15  
14  
DAV  
OTR  
MSB  
SHA OUT  
26 BPO/UPO  
24  
21  
REF IN  
666  
714  
769  
833  
909  
1000  
1111  
1250  
SAMPLING FREQUENCY – kHz  
REF OUT  
1µF  
Figure 6. Spurious Free Dynamic Range vs. Sampling  
Rate, fIN = 100 kHz  
*GROUND PLANE RECOMMENDED  
Figure 8. AD1671 Grounding and Decoupling  
–8–  
REV. B