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5962-9312601MXA 参数 Datasheet PDF下载

5962-9312601MXA图片预览
型号: 5962-9312601MXA
PDF下载: 下载PDF文件 查看货源
内容描述: [Complete 12-Bit 1.25 MSPS Monolithic A/D Converter]
分类和应用: 信息通信管理转换器
文件页数/大小: 16 页 / 393 K
品牌: ADI [ ADI ]
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AD1671  
Table III. Output Data Format  
Input  
Range  
Analog  
Inputl  
Digital  
Output  
Coding  
OTR2  
0 V to +2.5 V  
Straight Binary  
0 V  
+2.5 V  
+2.5003 V  
–0.0003 V  
0000 0000 0000  
0000 0000 0000  
1111 1111 1111  
1111 1111 1111  
1
0
0
1
0 V to +5 V  
Straight Binary  
–0.0006 V  
0 V  
+5 V  
0000 0000 0000  
0000 0000 0000  
1111 1111 1111  
1111 1111 1111  
1
0
0
1
+5.0006 V  
–2.5 V to +2.5 V Offset Binary  
–2.5006 V  
–2.5 V  
+2.5 V  
0000 0000 0000  
0000 0000 0000  
1111 1111 1111  
1111 1111 1111  
1
0
0
1
+2.4994 V  
–5 V to +5 V  
Offset Binary  
–5.0012 V  
–5 V  
+5 V  
0000 0000 0000  
0000 0000 0000  
1111 1111 1111  
1111 1111 1111  
1
0
0
1
+4.9988 V  
–2.5 V to +2.5 V Twos Complement –2.5006 V  
1000 0000 0000  
1000 0000 0000  
0111 1111 1111  
0111 1111 1111  
1
0
0
1
(Using MSB)  
–2.5 V  
+2.5 V  
+2.4994 V  
–5 V to +5 V  
Twos Complement –5.0012 V  
1000 0000 0000  
1000 0000 0000  
0111 1111 1111  
0111 1111 1111  
1
0
0
1
(Using MSB)  
–5 V  
+5 V  
+4.9988 V  
NOTES  
1Voltages listed are with offset and gain errors adjusted to zero.  
2Typical performance.  
connected to +5 V. It is possible to connect REF OUT to +5 V  
due to its output circuit implementation which shuts down the  
reference.  
OUTPUT DATA FORMAT  
The AD1671 provides both MSB and MSB outputs, delivering  
data in positive true straight binary for unipolar input ranges  
and positive true offset binary or twos complement for bipolar  
input ranges. Straight binary coding is used for systems that ac-  
cept positive-only signals. If straight binary coding is used with  
bipolar input signals, a 0 V input would result in a binary output  
of 2048. The application software would have to subtract 2048  
to determine the true input voltage. Host registers typically per-  
form math on signed integers and assume data is in that format.  
Twos complement format minimizes software overhead which is  
especially important in high speed data transfers, such as a  
DMA operation. The CPU is not bogged down performing data  
conversion steps, hence the total system throughput is increased.  
ILOGIC VS. CONVERSION RATE  
Figure 15 is the typical logic supply current vs. conversion rate  
for various capacitor loads on the digital outputs.  
6.5  
6.0  
5.5  
5.0  
4.5  
4.0  
3.5  
3.0  
2.5  
2.0  
1.5  
CL = 50pF  
OPTIONAL EXTERNAL REFERENCE  
The AD1671 includes an onboard +2.5 V reference. The refer-  
ence input pin (REF IN) can be connected to reference output  
pin (REF OUT) or a standard external +2.5 V reference can be  
selected to meet specific system requirements. Fast switching in-  
put dependent currents are modulated at the reference input.  
The reference input voltage can be held with the use of a capaci-  
tor. To prevent the AD1671’s onboard reference from oscil-  
lating when not connected to REF IN, REF OUT must be  
CL = 30pF  
CL = 0pF  
1.0  
0.5  
1k  
10k  
100k  
1M  
CONVERSION RATE – Hz  
Figure 15. ILOGIC vs. Conversion Rate for Various  
Capacitive Loads on the Digital Outputs  
REV. B  
–11–  
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