AD1671
APPLICATIONS
AD1671 TO ADSP-2101/2102
AD1671 TO ADSP-2100A
Figure 17 is identical to the 2100A interface except the sam-
pling clock is used to generate an interrupt (IRQ2) for the pro-
cessor. Upon interrupt the ADSP-2100A starts a data memory
read by providing an address on the address (A) bus. The de-
code address generates OE for the D-latches and the processor
reads their output over the Data (D) bus. Reading the conver-
sion result is thus completed within a single processor cycle.
Figure 16 demonstrates the AD1671 to ADSP-2100A interface.
The 2100A with a clock frequency of 12.5 MHz can execute an
instruction in one 80 ns cycle. The AD1671 is configured to
perform continuous time sampling. The DAV output of the
AD1671 is asserted at the end of each conversion. DAV can be
used to latch the conversion result into the two 574 octal
D-latches. The falling edge of the sampling clock is used to
generate an interrupt (IRQ3) for the processor. Upon interrupt,
the ADSP-2100A starts a data memory read by providing an
address on the DMA bus. The decoded address generates OE
for the latches and the processor reads their output over the
DMA bus. The conversion result is read within a single proces-
sor cycle.
RD
DAV
OE
A0:13
574
ADDRESS BUS
DECODE
8
Q0:7
AD1671
8
D0:7
ADSP-2101
OE
BIT1:12
16
574
D0:3
D0:15
DATA BUS
DMRD
4
OE
DAV
8
574
DMA0:13 ADDRESS BUS
Q0:7
8
4
D0:7
Q0:7
8
AD1671
SAMPLING
CLOCK
DECODE
IRQ2
ENCODE
D0:7
ADSP-
2100A
BIT1:12
OE
16
Figure 17. AD1671 to ADSP-2101/ADSP-2102 Interface
574
DMA0:15
DMACK
DATA BUS
4
D0:3
Q0:7
D0:7
8
+5V
4
SAMPLING
CLOCK
IRQ3
ENCODE
Figure 16. AD1671 to ADSP-2100A Interface
–12–
REV. B
ADI [ ADI ]
