AD7870/AD7875/AD7876
1, 2
(V = +5 V ؎ 5%, V = –5 V ؎ 5%, AGND = DGND = 0 V. See Figures 9, 10, 11 and 12.)
TIMING CHARACTERISTICS
DD
SS
Lim it at TMIN, TMAX
Lim it at TMIN, TMAX
(S, T Versions)
P aram eter
(J, K, L, A, B, C Versions)
Units
Conditions/Com m ents
t1
t2
t3
t4
t53
t64
t7
50
0
60
0
70
57
5
50
0
50
0
75
0
70
70
5
50
0
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns max
ns min
ns min
ns min
ns min
ns max
ns min
ns max
ns min
ns max
ns min
ns max
ns min
ns min
ns min
ns min
CONVST Pulse Width
CS to RD Setup T ime (Mode 1)
RD Pulse Width
CS to RD Hold T ime (Mode 1)
RD to INT Delay
Data Access T ime after RD
Bus Relinquish T ime after RD
t8
t9
t10
t11
t12
t13
HBEN to RD Setup T ime
HBEN to RD Hold T ime
SSTRB to SCLK Falling Edge Setup T ime
SCLK Cycle T ime
SCLK to Valid Data Delay. CL = 35 pF
SCLK Rising Edge to SSTRB
0
0
100
370
135
20
100
10
100
60
120
200
0
100
370
150
20
100
10
100
60
120
200
0
5
6
t14
Bus Relinquish T ime after SCLK
t15
t16
t17
t18
t19
t20
CS to RD Setup T ime (Mode 2)
CS to BUSY Propagation Delay
Data Setup T ime Prior to BUSY
CS to RD Hold T ime (Mode 2)
HBEN to CS Setup T ime
0
0
0
0
HBEN to CS Hold T ime
NOT ES
1T iming specifications in bold pr int are 100% production tested. All other times are sample tested at +25 °C to ensure compliance. All input signals are
specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2Serial timing is measured with a 4.7 kΩ pull-up resistor on SDAT A and SSTRB and a 2 kΩ pull-up on SCLK. T he capacitance on all three outputs is 35 pF.
3t6 is measured with the load circuits of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
4t7 is defined as the time required for the data lines to change 0.5 V when loaded with the circuits of Figure 2.
5SCLK mark/space ratio (measured from a voltage level of 1.6 V) is 40/60 to 60/40.
6SDAT A will drive higher capacitive loads but this will add to t 12 since it increases the external RC time constant (4.7 kΩʈCL) and hence the time to reach 2.4 V.
Specifications subject to chance without notice.
ABSO LUTE MAXIMUM RATINGS*
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
VSS to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –7 V
AGND to DGND . . . . . . . . . . . . . . . . . –0.3 V to VDD +0.3 V
VIN to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –15 V to +15 V
REF OUT to AGND . . . . . . . . . . . . . . . . . . . . . . . . 0 V to VDD
Digital Inputs to DGND . . . . . . . . . . . . –0.3 V to VDD +0.3 V
Digital Outputs to DGND . . . . . . . . . . . –0.3 V to VDD +0.3 V
Operating T emperature Range
Commercial (J, K, L Versions – AD7870) . . . 0°C to +70°C
a. High-Z to VOH
b. High-Z to VOL
Commercial (K, L Versions – AD7875) . . . . . 0°C to +70°C
Industrial (A, B, C Versions – AD7870) . . . . –25°C to +85°C
Industrial (B, C Versions – AD7875/AD7876)
Figure 1. Load Circuits for Access Tim e
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Extended (S, T Versions) . . . . . . . . . . . . . . –55°C to +125°C
Storage T emperature Range . . . . . . . . . . . . . –65°C to +150°C
Lead T emperature (Soldering, 10 sec) . . . . . . . . . . . . . +300°C
Power Dissipation (Any Package) to +75°C . . . . . . . . . 450 mW
Derates above +75°C by . . . . . . . . . . . . . . . . . . . . . 10 mW/°C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. T his is a stress rating only; functional
operation of the device at these or any other conditions above those listed in
the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
device reliability.
a. VOH to High-Z
b. VOL to High-Z
Figure 2. Load Circuits for Output Float Delay
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7870/AD7875/AD7876 feature proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. B
–4–
ADI [ ADI ]
