(V = +5 V ؎ 5%, V = –5 V ؎ 5%,
A6ND = DGND = 0 V, fCLK = 2.5 MHz external, unless otherwise stated. All Specifications T to Tmax unless otherwise noted.)
AD7870/AD7875/AD7876–SPECIFICATIONS
DD
SS
min
AD 7870
P aram eter
J, Al K, Bl L, Cl Sl
Tl
Units
Test Conditions/Com m ents
DYNAMIC PERFORMANCE2
Signal to Noise Ratio3 (SNR)
@ +25°C
T MIN to T MAX
T otal Harmonic Distortion (T HD)
70
70
–80
70
70
–80
72
71
–80
69
69
–78
69
69
–78
dB min
dB min
dB max
VIN = 10 kHz Sine Wave, fSAMPLE = 100 kHz
T ypically 71.5 dB for 0 < VIN < 50 kHz
VIN = 10 kHz Sine Wave, fSAMPLE = 100 kHz
T ypically –86 dB for 0 < VIN < 50 kHz
VIN = 10 kHz, fSAMPLE = 100 kHz
Peak Harmonic or Spurious Noise
–80
–80
–80
–78
–78
dB max
T ypically –86 dB for 0 < VIN < 50 kHz
Intermodulation Distortion (IMD)
Second Order T erms
T hird Order T erms
–80
–80
2
–80
–80
2
–80
–80
2
–78
–78
2
–78
–78
2
dB max
dB max
µs max
fa = 9 kHz, fb = 9.5 kHz, fSAMPLE = 50 kHz
fa = 9 kHz, fb = 9.5 kHz, fSAMPLE = 50 kHz
T rack/Hold Acquisition T ime
DC ACCURACY
Resolution
12
12
12
12
12
12
12
Bits
Minimum Resolution for which
No Missing Codes are Guaranteed
Integral Nonlinearity
12
±1/2
12
12
Bits
±1/2
±1
±1
±5
±5
±5
±1/4 ±1/2
±1/2
±1
±5
±5
±5
±1/2
±1
±1
±5
±5
±5
LSB typ
LSB max
LSB max
LSB max
LSB max
LSB max
Integral Nonlinearity
Differential Nonlinearity
Bipolar Zero Error
±5
±5
±5
±5
±5
±5
Positive Full-Scale Error4
Negative Full-Scale Error4
ANALOG INPUT
Input Voltage Range
Input Current
±3
±3
±3
±3
±3
Volts
µA max
±500 ±500
±500 ±500 ±500
REFERENCE OUT PUT
REF OUT @ +25°C
2.99
3.01
±60
2.99
3.01
±60
±1
2.99 2.99
3.01 3.01
±35 ±60
2.99
3.01
±35
±1
V min
V max
ppm/°C max
mV max
REF OUT T empco
Reference Load Sensitivity (∆REF OUT /∆I) ±1
±1
±1
Reference Load Current Change (0–500 µA)
Reference Load Should Not Be Changed
During Conversion.
LOGIC INPUT S
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
2.4
0.8
±10
±10
10
2.4
0.8
±10
±10
10
2.4
0.8
±10 ±10
±10 ±10
2.4
0.8
2.4
0.8
±10
±10
10
V min
VDD = 5 V ± 5%
VDD = 5 V ± 5%
VIN = 0 V to VDD
VIN = VSS to VDD
V max
µA max
µA max
pF max
Input Current (12/8/CLK Input Only)
5
Input Capacitance, CIN
10
10
LOGIC OUT PUT S
Output High Voltage, VOH
Output Low Voltage, VOL
DB11–DB0
4.0
0.4
4.0
0.4
4.0
0.4
4.0
0.4
4.0
0.4
V min
V max
ISOURCE = 40 µA
ISINK = 1.6 mA
Floating-State Leakage Current
Floating-State Output Capacitance5
±10
15
±10
15
±10 ±10
±10
15
µA max
pF max
15
15
CONVERSION T IME
External Clock (fCLK = 2.5 MHz)
Internal Clock
8
7/9
8
7/9
8
7/9
8
7/9
8
7/9
µs max
µs min/µs max
POWER REQUIREMENT S
VDD
VSS
IDD
ISS
+5
–5
13
6
+5
–5
13
6
+5
–5
13
6
+5
–5
13
6
+5
–5
13
6
V nom
V nom
mA max
mA max
mW max
±5% for Specified Performance
±5% for Specified Performance
T ypically 8 mA
T ypically 4 mA
T ypically 60 mW
Power Dissipation
95
95
95
95
95
NOT ES
1T emperature ranges are as follows: J, K, L Versions; 0°C to +70°C: A, B, C Versions; –25°C to +85°C: S, T Versions; –55°C to +125°C.
2VIN (pk-pk) = ±3 V.
3SNR calculation includes distortion and noise components.
4Measured with respect to internal reference and includes bipolar offset error.
5Sample tested @ +25°C to ensure compliance.
Specifications subject to change without notice.
–2–
REV. B
ADI [ ADI ]
