AD7846
MICROPROCESSOR INTERFACING
AD7846-TO-8086 INTERFACE
AD7846-TO-MC68000 INTERFACE
Figure 26 shows the 8086 16-bit processor interfacing to the
AD7846. The double buffering feature of the DAC is not used in
Interfacing between the AD7846 and MC68000 is accomplished
using the circuit of Figure 28. The following routine writes data
to the DAC latches and then outputs the data via the DAC latch.
LDAC
this circuit because
is permanently tied to 0 V. AD0 to
AD15 (the 16-bit data bus) are connected to the DAC data bus
(DB0 to DB15). The 16-bit word is written to the DAC in one
MOV instruction and the analog output responds immediately.
In this example, the DAC address is 0xD000.
1000 MOVE.W
#W,
D0
The desired DAC data,
W, is loaded into
Data Register 0. W
may be any value
ADDRESS BUS
between 0 and 65535
(decimal) or 0 and
FFFF (hexadecimal).
ADDRESS
CS
DECODE
16-BIT
LATCH
LDAC
ALE
8086
MOVE.W
D0,
The data, W, is
$E000 transferred between
D0 and the DAC
+5V
CLR
DEN
RD
AD7846*
register.
R/W
WR
MOVE.W
TRAP
#228, Control is returned
DATA BUS
AD0 TO AD15
DB0 TO DB15
D7
to the System Monitor
using these two
instructions.
#14
*LINEAR CIRCUITRY OMITTED FOR CLARITY
Figure 26. AD7846-to-8086 Interface Circuit
In a multiple DAC system, the double buffering of the AD7846
allows the user to simultaneously update all DACs. In Figure 27,
a 16-bit word is loaded to the input latches of each of the DACs
in sequence. Then, with one instruction to the appropriate
A1 TO A23
ADDRESS BUS
MC68000
DS
ADDRESS
DECODE
CS
+5V
CLR
DTACK
LDAC
CS4
LDAC
address,
(that is,
) is brought low, updating all the
AD7846*
R/W
DACs simultaneously.
R/W
ADDRESS BUS
DATA BUS
D0 TO D15
DB0 TO DB15
ADDRESS
CS
*LINEAR CIRCUITRY OMITTED FOR CLARITY
DECODE
16-BIT
LATCH
ALE
Figure 28. AD7846-to-MC68000 Interface
8086
LDAC
DEN
RD
AD7846*
R/W
WR
CLR
+5V
AD0 TO AD15
DATA BUS
DB0 TO DB15
CS
AD7846*
LDAC
R/W
CLR
+5V
DB0 TO DB15
CS
AD7846*
LDAC
R/W
CLR
+5V
DB0 TO DB15
*LINEAR CIRCUITRY OMITTED FOR CLARITY
Figure 27. AD7846-to-8086 Interface: Multiple DAC System
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