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5962-89697013A 参数 Datasheet PDF下载

5962-89697013A图片预览
型号: 5962-89697013A
PDF下载: 下载PDF文件 查看货源
内容描述: LC2MOS 16位电压输出DAC [LC2MOS 16-Bit Voltage Output DAC]
分类和应用:
文件页数/大小: 24 页 / 451 K
品牌: ADI [ ADI ]
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AD7846  
BIPOLAR OPERATION  
Figure 24 shows the AD7846 set up for 10 V bipolar operation.  
The AD588 provides precision 5 V tracking outputs that are  
fed to the VREF+ and VREF− inputs of the AD7846. The code table  
for Figure 24 is shown in Table 9.  
Full-scale and bipolar zero adjustment are provided by varying  
the gain and balance on the AD588. R2 varies the gain on the  
AD588 while R3 adjusts the +5 V and −5 V outputs together  
with respect to ground.  
+15V  
+15V  
+5V  
For bipolar zero adjustment on the AD7846, load the DAC with  
100…000 and adjust R3 until VOUT = 0 V. Full scale is adjusted  
R1  
39kΩ  
4
21  
4
6
by loading the DAC with all 1s and adjusting R2 until VOUT  
=
V
V
CC  
DD  
+15V  
2
3
1
7
9
9.999694 V.  
C1  
V
V
V
V
5
7
8
OUT  
REF+  
OUT  
1µF  
(–10V TO +10V)  
When bipolar zero and full-scale adjustment are not needed, R2  
and R3 can be omitted, Pin 12 on the AD588 should be connected  
to Pin 11, and Pin 5 should be left floating. If a user wants a 5 V  
output range, there are two choices. By tying Pin 6 (RIN) of the  
AD7846 to VOUT (Pin 5), the output stage gain is reduced to  
unity and the output range is 5 V. If only a positive 5 V reference  
is available, bipolar 5 V operation is still possible. Tie VREF− to  
0 V and connect RIN to VREF+. This also gives a 5 V output  
range. However, the linearity, gain, and offset error specifications  
are the same as the unipolar 0 V to 5 V range.  
AD588  
AD7846*  
R2  
10kΩ  
5
R
6
IN  
14  
15  
16  
10  
11  
REF–  
20  
DGND  
–15V  
SIGNAL  
GROUND  
V
SS  
12  
8
13  
9
R3  
100kΩ  
–15V  
*ADDITIONAL PINS OMITTED FOR CLARITY  
Figure 24. Bipolar 10 V Operation  
Table 9. Offset Binary Code Table for Figure 24  
Binary Number in DAC ꢀatch  
MUꢀTIPꢀYING OPERATION  
The AD7846 is a full multiplying DAC. To obtain four-quadrant  
multiplication, tie VREF− to 0 V, apply the ac input to VREF+, and  
tie RIN to VREF+. Figure 11 shows the large signal frequency  
response when the DAC is used in this fashion.  
ꢀSB1  
Analog Output (VOUT  
)
MSB  
1111 1111 1111 1111  
1000 0000 0000 0001  
1000 0000 0000 0000  
0111 1111 1111 1111  
0000 0000 0000 0000  
+10 (32,767/32,76±) V  
+10 (1/32,76±) V  
0 V  
−10 (1/32,76±) V  
−10 (32,76±/32,76±) V  
1 LSB = 10 V/215 = 10 V/32,76± = 305 μV.  
Rev. G | Page 14 of 24  
 
 
 
 
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