AD7846
V
REF+
SEGMENT 16
R
R
DAC1
DAC2
R
V
IN
S1
S3
S2
S4
DAC3
A1
A2
A3
OUT
12-BIT DAC
S15
S17
S14
S16
DB11 TO DB0
DB15 TO DB12
DB15 TO DB12
SEGMENT 1
V
REF–
Figure 21. Digital-to-Analog Conversion
operation. Figure 13 and Figure 14 show the outputs of the
AD7846 without and with the deglitcher.
OUTPUT STAGE
The output stage of the AD7846 is shown in Figure 22. It is capable
of driving a 2 kΩ/1000 pF load. It also has a resistor feedback
network that allows the user to configure it for gains of 1 or 2.
Table 6 shows the different output ranges that are possible.
R
IN
10kΩ
10kΩ
C1
An additional feature is that the output buffer is configured as a
track-and-hold amplifier. Although normally tracking its input,
this amplifier is placed in a hold mode for approximately 2.5 μs
V
OUT
DAC3
LDAC
after the leading edge of
. This short state keeps the DAC
ONE
SHOT
output at its previous voltage while the AD7846 is internally
changing to its new value. Thus, any glitches that occur in the
transition are not seen at the output. In systems where the
LDAC
LDAC
is tied permanently low, the deglitching is not in
Figure 22. Output Stage
Rev. G | Page 12 of 24
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