AD7824/AD7828
TIMING CHARACTERISTICS1
(VDD = 5 V; VREF(+) = 5 V; VREF(–) = GND = 0 V, unless otherwise noted.)
Limit at 25؇C
Limit at TMIN, TMAX
Limit at TMIN, TMAX
Parameter
(All Grades)
(K, L, B, C Grades)
(T, U Grades)
Unit
Conditions/Comments
tCSS
tCSH
tAS
tAH
tRDY
0
0
0
30
40
0
0
0
35
60
0
0
0
40
60
ns min
ns min
ns min
ns min
ns max
CS to RD Setup Time
CS to RD Hold Time
Multiplexer Address Setup Time
Multiplexer Address Hold Time
CS to RDY Delay. Pull-Up
Resistor 5 kΩ.
Conversion Time, Mode 0
Data Access Time after RD
Data Access Time after INT, Mode 0
RD to INT Delay
2
tCRD
tACC1
tACC2
tlNTH
2.0
85
50
2.4
110
60
2.8
120
70
µs max
ns max
ns max
ns typ
3
3
2
40
65
70
75
60
500
60
600
100
70
500
80
100
70
600
80
ns max
ns max
ns min
ns min
ns max
4
tDH
tP
tRD
Data Hold Time
Delay Time between Conversions
Read Pulsewidth, Mode 1
500
400
NOTES
1Sample tested at 25°C to ensure compliance. All input control signals are specified with tRISE = tFALL = 20 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2CL = 50 pF.
3Measured with load circuits of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
4Defined as the time required for the data lines to change 0.5 V when loaded with the circuits of Figure 2.
Specifications subject to change without notice.
Test Circuits
DBN
DBN
3k⍀
10pF
3k⍀
100pF
DGND
DGND
a. VOH to High-Z
a. High-Z to VOH
5V
5V
3k⍀
3k⍀
DBN
DBN
10pF
DGND
100pF
DGND
b. VOL to High-Z
b. High-Z to VOL
Figure 2. Load Circuits for Data Hold Time Test
Figure 1. Load Circuits for Data Access Time Test
REV. F
–3–
ADI [ ADI ]
