AD7824/AD7828
UNIPOLAR OPERATION
25k⍀
The analog input range for any channel of the AD7824/AD7828 is
0 V to 5 V as shown in the unipolar operational diagram of
Figure 10. Figure 11 shows the designed code transitions that
occur midway between successive integer LSB values (i.e., 1/2 LSB,
3/2 LSB, 5/2 LSB, FS 3/2 LSBs). The output code is natural
binary with 1 LSB = FS/256 = (5/256) V = 19.5 mV.
40k⍀
27k⍀
V
IN
AD544
AIN1
AD7824*
AD7828*
5V
12k⍀
5V
V
(+)
REF
5V
V
DD
0.1F
47F
DB7
DB0
V
(–)
REF
GND
5V
V
DD
0.1F
47F
V
REF
5V
V
(+)
(–)
REF
AIN1
*ADDITIONAL PINS OMITTED FOR CLARITY.
ONLY CHANNEL 1 SHOWN.
AD7824*
AD7828*
V
IN
0VTO 5V
DB7
Figure 12. AD7824/AD7828 Bipolar 4 V Operation
V
REF
GND
DB0
11111111
FS = 8V
1LSB = FS/256
*ADDITIONAL PINS OMITTED FOR CLARITY.
11111110
11111101
10000010
10000001
ONLY CHANNEL 1 SHOWN.
Figure 10. AD7824/AD7828 Unipolar 0 V to 5 V Operation
+FS
2
FULL-SCALE
TRANSITION
10000000
01111111
–FS
2
+ 1LSB
11111111
11111110
11111101
01111110
00000010
00000001
00000000
FS
1LSB =
256
0V
AIN, INPUTVOLTAGE – LSB
00000011
00000010
00000001
00000000
Figure 13. Ideal Input/Output Transfer Characteristic for
4 V Operation
TIMING AND CONTROL
0
1LSB 2LSB 3LSB
AIN, INPUTVOLTAGE – LSB
FS
FS – 1LSB
The AD7824/AD7828 has two digital inputs for timing and
control. These are Chip Select (CS) and Read (RD). A READ
operation brings CS and RD low, which starts a conversion on
the channel selected by the multiplexer address inputs (see
Table I). There are two modes of operation as outlined by the
timing diagrams of Figures 14 and 15. Mode 0 is designed for
microprocessors that can be driven into a WAIT state. A
READ operation (i.e., CS and RD are taken low) starts a con-
version and data is read when conversion is complete. Mode l
does not require microprocessor WAIT states. A READ operation
initiates a conversion and reads the previous conversion results.
Figure 11. Ideal Input/Output Transfer Characteristic for
Unipolar 0 V to 5 V Operation
BIPOLAR OPERATION
The circuit of Figure 12 is designed for bipolar operation. An
AD544 op amp conditions the signal input (VIN) so that only
positive voltages appear at AIN1. The closed loop transfer func-
tion of the op amp for the resistor values shown is given below:
AIN1 = 2.5 − 0.625V Volts
(
)
IN
Table I. Truth Table for Input Channel Selection
The analog input range is 4 V and the LSB size is 31.25 mV.
The output code is complementary offset binary. The ideal
input/output characteristic is shown in Figure 13.
AD7824
AD7828
A1 A0
A1
A0
A2
Channel
0
0
1
1
0
1
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
–8–
REV. F
ADI [ ADI ]
