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5962-8850501RA 参数 Datasheet PDF下载

5962-8850501RA图片预览
型号: 5962-8850501RA
PDF下载: 下载PDF文件 查看货源
内容描述: 10位A / D转换器 [10-Bit A/D Converter]
分类和应用: 转换器模数转换器
文件页数/大小: 10 页 / 593 K
品牌: ADI [ ADI ]
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AD573  
It is also possible to write a faster-executing assembly-language  
routine to control the AD573. Such a routine will require a de-  
lay between starting and reading the converter. This can be eas-  
ily implemented by calling the Apple’s WAIT subroutine (which  
resides at location $FCA8) after loading the accumulator with a  
number greater than or equal to two.  
8085-Series Microprocessor Interface  
The AD573 can also be used with 8085-series microprocessors.  
These processors use separate control signals for RD and WR,  
as opposed to the single R/W control signal used in the 6800/  
6500 series processors.  
There are two constraints related to operation of the AD573  
with 8085-series processors. The first problem is the width of  
the CONVERT pulse. The circuit shown in Figure 17 (essen-  
tially the same as that shown in Figure 13) will produce a wide  
enough CONVERT pulse when the 8085 is running at 5 MHz.  
For 8085 systems running at slower clock rates (3 MHz), the  
flip-flop-based circuit can be eliminated since the WR pulse will  
be approximately 500 ns wide.  
The other consideration is the access time of the AD573’s three-  
state output data buffers, which is 250 ns maximum. It may be  
necessary to insert wait states during RD operations from the  
AD573. This will not be a problem in systems using memories  
with comparable access times, since wait states will have already  
been provided in the basic system design.  
Figure 17. AD573–8085A Interface Connections  
The following assembly-language subroutine can be used to  
control an AD573 residing at memory locations 3000H and  
3001H. The 10 bits of data are returned (left-justified) in the  
DE register pair.  
ADC: LXI H, 3000 ; LOAD HL WITH AD573 ADDRESS  
MOV M, A ; START CONVERSION  
MVI B, 06  
LOOP: DCR B  
JNZ LOOP  
; LOAD DELAY PERIOD  
; DELAY LOOP  
;
MOV A, M ; READ LOW BYTE  
ANI C0  
MOV E, A  
INR L  
; MASK LOWER 6 BITS  
; STORE CLEAN LOW BYTE IN E  
; LOAD HIGH BYTE ADDRESS  
MOV D, M ; MOVE HIGH BYTE TO D  
RET ; EXIT  
REV. B  
–8–