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5962-8850501RA 参数 Datasheet PDF下载

5962-8850501RA图片预览
型号: 5962-8850501RA
PDF下载: 下载PDF文件 查看货源
内容描述: 10位A / D转换器 [10-Bit A/D Converter]
分类和应用: 转换器模数转换器
文件页数/大小: 10 页 / 593 K
品牌: ADI [ ADI ]
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AD573  
BIPOLAR CONNECTION  
To obtain the bipolar –5 V to +5 V range with an offset binary  
output code, the bipolar offset control pin is left open.  
SAMPLE-HOLD AMPLIFIER CONNECTION TO THE  
AD573  
Many situations in high speed acquisition systems or digitizing  
rapidly changing signals require a sample-hold amplifier (SHA)  
in front of the A/D converter. The SHA can acquire and hold a  
signal faster than the converter can perform a conversion. A  
SHA can also be used to accurately define the exact point in  
time at which the signal is sampled. For the AD573, a SHA can  
also serve as a high input impedance buffer.  
A –5.000 volt signal will give a 10-bit code of 00000000 00; an  
input of 0.000 volts results in an output code of 10000000 00  
and +4.99 volts at the input yields the 11111111 11 code. The  
nominal transfer curve is shown in Figure 6.  
Figure 8 shows the AD573 connected to the AD582 monolithic  
SHA for high speed signal acquisition. In this configuration, the  
AD582 will acquire a 10 volt signal in less than 10 µs with a  
droop rate less than 100 µV/ms.  
Figure 6. AD573 Transfer Curve— Bipolar Operation  
Note that in the bipolar mode, the code transitions are offset  
1/2 LSB such that an input voltage of 0 volts ±5 mV yields the  
code representing zero (10000000 00). Each output code is then  
centered on its nominal input voltage.  
Full-Scale Calibration  
Full-Scale Calibration is accomplished in the same manner as in  
unipolar operation except the full scale input voltage is +4.985  
volts.  
Negative Full-Scale Calibration  
Figure 8. Sample-Hold Interface to the AD573  
The circuit in Figure 4a can also be used in bipolar operation to  
offset the input voltage (nominally –5 V) which results in the  
00000000 00 code. R2 should be omitted to obtain a symmetri-  
cal range.  
DR goes high after the conversion is initiated to indicate that  
reset of the SAR is complete. In Figure 8 it is also used to put  
the AD582 into the hold mode while the AD573 begins its con-  
version cycle. (The AD582 settles to final value well in advance  
of the first comparator decision inside the AD573).  
The bipolar offset control input is not directly TTL compatible  
but a TTL interface for logic control can be constructed as  
shown in Figure 7.  
DR goes low when the conversion is complete placing the  
AD582 back in the sample mode. Configured as shown in Fig-  
ure 8, the next conversion can be initiated after a 10 µs delay to  
allow for signal acquisition by the AD582.  
Observe carefully the ground, supply, and bypass capacitor con-  
nections between the two devices. This will minimize ground  
noise and interference during the conversion cycle.  
GROUNDING CONSIDERATIONS  
The AD573 provides separate Analog and Digital Common  
connections. The circuit will operate properly with as much as  
±200 mV of common-mode voltage between the two commons.  
This permits more flexible control of system common bussing  
and digital and analog returns.  
In normal operation, the Analog Common terminal may gener-  
ate transient currents of up to 2 mA during a conversion. In ad-  
dition a static current of about 2 mA will flow into Analog  
Common in the unipolar mode after a conversion is complete.  
The Analog Common current will be modulated by the varia-  
tions in input signal.  
Figure 7. Bipolar Offset Controlled by Logic Gate  
Gate Output = 1 Unipolar 0–10 V Input Range  
Gate Output = 0 Bipolar ±5 V Input Range  
The absolute maximum voltage rating between the two com-  
mons is ±1 volt. It is recommended that a parallel pair of  
back-to-back protection diodes be connected between the com-  
mons if they are not connected locally.  
REV. B  
–5–