欢迎访问ic37.com |
会员登录 免费注册
发布采购

5962-8850501RA 参数 Datasheet PDF下载

5962-8850501RA图片预览
型号: 5962-8850501RA
PDF下载: 下载PDF文件 查看货源
内容描述: 10位A / D转换器 [10-Bit A/D Converter]
分类和应用: 转换器模数转换器
文件页数/大小: 10 页 / 593 K
品牌: ADI [ ADI ]
 浏览型号5962-8850501RA的Datasheet PDF文件第2页浏览型号5962-8850501RA的Datasheet PDF文件第3页浏览型号5962-8850501RA的Datasheet PDF文件第4页浏览型号5962-8850501RA的Datasheet PDF文件第5页浏览型号5962-8850501RA的Datasheet PDF文件第6页浏览型号5962-8850501RA的Datasheet PDF文件第8页浏览型号5962-8850501RA的Datasheet PDF文件第9页浏览型号5962-8850501RA的Datasheet PDF文件第10页  
AD573  
CONVERT Pulse Generation  
This mode is particularly useful for bench-testing of the AD573,  
and in applications where dedicated I/O ports of peripheral in-  
terface adapter chips are available.  
The AD573 is tested with a CONVERT pulse width of 500 ns  
and will typically operate with a pulse as short as 300 ns.  
However, some microprocessors produce active WR pulses  
which are shorter than this. Either of the circuits shown in Fig-  
ure 13 can be used to generate an adequate CONVERT pulse  
for the AD573.  
In both circuits, the short low going WR pulse sets the  
CONVERT line high through a flip-flop. The rising edge of  
DR (which signifies that the internal logic has been reset) resets  
the flip-flop and brings CONVERT low, which starts the  
conversion.  
Figure 15. AD573 in “Stand-Alone“ Mode  
(Output Data Valid 500 ns After DR Goes Low)  
Note that tDSC is slightly longer when the result of the previous  
conversion contains a Logic 1 on the LSB. This means that the  
actual CONVERT pulse generated by the circuits in Figure 13  
will vary slightly in width.  
Apple II Microcomputer Interface  
The AD573 can provide a flexible, low cost analog interface for  
the popular Apple II microcomputer. The Apple II, based on a  
1 MHz 6502 microprocessor, meets all timing requirements for  
the AD573. Only a few TTL gates are required to decode the  
signals available on the Apple II’s peripheral connector. The  
recommended connections are shown in Figure 16.  
Figure 13a. Using 74LS00  
Figure 13b. Using 1/2 74LS74  
Output Data Format  
The AD573 output data is presented in a left justified format.  
The 8 MSBs (DB9–DB2, Pins 10 through 3) are enabled by  
HBE (Pin 20) and the 2 LSBs (DB1, DB0—Pins 2 and 1) are  
enabled by LBE (Pin 19). This allows simple interface to 8-bit  
system buses by overlapping the 2 MSBs and the 2 LSBs. The  
organization of the data is shown in Figure 14.  
When the least significant bits are read (LBE brought low), the  
six remaining bits of the byte will contain meaningless data.  
These unwanted bits can be masked by logically ANDing the  
byte with 11000000 (C0 hex), which forces the 6 lower bits to  
Logic 0 while preserving the two most significant bits of the byte.  
Note that it is not possible to reconfigure the AD573 for right  
justified data.  
Figure 16. AD573 Interface to Apple ll  
The BASIC routine listed here will operate the AD573 circuit  
shown in Figure 16. The conversion is started by POKEing to  
the location which contains the AD573. The relatively slow ex-  
ecution speed of BASIC eliminates the need for a delay routine  
between starting and reading the converter. This routine as-  
sumes that the AD573 is connected for a ±5 volt input range.  
Variable I represents the integer value (from 0 to 1023) read  
from the AD573. Variable V represents the actual value of the  
input signal (in volts).  
Figure 14. AD573 Output Data Format  
In systems where all 10 bits are desired at the same time, HBE  
and LBE may be tied together. This is useful in interfacing to  
16-bit bus systems. The resulting 10-bit word can then be  
placed at the high end of the 16-bit bus for left justification or at  
the low end for right justification.  
It is also possible to use the AD573 in a “stand-alone” mode,  
where the output data buffers are automatically enabled at the  
end of a conversion cycle. In this mode, the DR output is wired  
to the HBE and LBE inputs. The outputs thus are forced into  
the high impedance state during the conversion period, and  
valid data becomes available approximately 500 ns after the DR  
signal goes low at the end of the conversion. The 500 ns delay  
allows propagation of the least significant bit through the inter-  
nal logic.  
100 PRINT “WHICH SLOT IS THE A/D IN”;:INPUT S  
110 A=49280 + 16*S  
120 POKE A,0  
130 L=PEEK(A) :H=PEEK(A+1)  
140 I =(4*H) + INT(L/64)  
150 V=(I/1024)*10-5  
160 PRINT “THE INPUT SIGNAL IS”;V;“VOLTS.”  
REV. B  
–7–