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5962-01-385-6686 参数 Datasheet PDF下载

5962-01-385-6686图片预览
型号: 5962-01-385-6686
PDF下载: 下载PDF文件 查看货源
内容描述: [IC,A/D CONVERTER,SINGLE,12-BIT,HYBRID,DIP,32PIN]
分类和应用: 光电二极管转换器
文件页数/大小: 12 页 / 368 K
品牌: ADI [ ADI ]
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AD578/AD579  
CLOCK RATE CONTROL  
J GRADE  
K,T GRADES  
The internal clock is preset to a nominal conversion time of 5.6 µs  
(AD578) or 4.8 µs (AD579). It can be adjusted for either faster  
or slower conversion rates. For faster conversions, connect the  
appropriate 1% resistor between Pins 17 and 18 and short Pin 18  
to Pin 19 (see Figures 6, 7, and 8).  
2.2s  
CONVERSION  
RATE  
1.8s  
CONVERSION  
RATE  
649⍀  
422⍀  
1%  
1%  
For slower conversions (AD578 only), connect a capacitor  
between Pins 15 and 17.  
Figure 8. AD579 Clock Rate Control Connection  
Note that the No Missing Code operation is not guaranteed  
when operating in this mode if a particular grades conversion  
speed specification is exceeded.  
Short Cycle InputA short cycle input, Pin 14, permits the  
timing cycle to be terminated after any number of desired bits  
has been converted, allowing shorter conversion times in appli-  
cations not requiring the full 10-bit (AD579) or 12-bit (AD578)  
resolution. Short cycle pin connections and associated conver-  
sion times are summarized in Tables III and IV.  
3s  
CONVERSION  
RATE  
6s  
CONVERSION  
RATE  
4.5s  
CONVERSION  
RATE  
L GRADE  
K,T GRADES  
J, S GRADES  
TO SLOW  
CONVERSION,  
USE C  
FROM  
FIGURE 7  
Table III. AD578 Short Cycle Connections  
825⍀  
؎1%  
3.32⍀  
؎1%  
Connect  
Pin 14 to  
Conversion Speed  
(s)  
For Resolution Bit  
Figure 6. AD578 Clock Rate Control Connection  
12  
10  
8
Pin 16  
Pin 2  
Pin 4  
3
2.5  
2
CAPACITANCE – pF  
1000  
680  
330  
13.0  
10.0  
8.0  
Table IV. AD579 Short Cycle Connections  
CAPACITOR  
RESISTOR  
Connect  
Pin 14 to  
Conversion Speed  
(s)  
For Resolution Bit  
10  
8
Pin 2  
Pin 4  
1.8  
1.5  
6.0  
4.0  
2.0  
External ClockAn external clock may be connected directly  
to the clock input, Pin 19. When operating in this mode, the  
convert start should be held high for a minimum of one clock  
period in order to reset the SAR and synchronize the conversion  
cycle. A positive-going pulse width of 100 ns to 200 ns will provide  
a continuous string of conversions that start on the first rising  
edge of the external clock after the EOC output has gone low.  
1.5  
10k  
200  
2k  
RESISTANCE –  
Figure 7. AD578 Conversion Times vs. R or C Values  
External Buffer AmplifierIn applications where the AD578 or  
AD579 is to be driven from high impedance sources or directly  
from an analog multiplexer, a fast slewing, wideband op amp like  
the AD711 should be used (see Figure 9).  
V
V
GND  
SS  
DD  
+5V +15V –15V  
+V  
AD711  
–V  
OUT  
ANALOG INPUT  
0V TO 10V  
S1  
AD7506  
S16  
DATA BITS  
1 TO 12  
A0 A1 A2 A3  
EN  
AD578  
OR  
AD579  
Figure 9. Input Buffer  
REV. C  
–9–