AD578/AD579
ORDERING GUIDE1
Conversion
Speed
Temperature
Range
Package
Option2
Model
Resolution
AD578JN (JD)
AD578KN (KD)
AD578LN (LD)
AD578SD
12 Bits
12 Bits
12 Bits
12 Bits
12 Bits
12 Bits
12 Bits
10 Bits
10 Bits
10 Bits
10 Bits
6.0 ms
4.5 ms
3.0 ms
6.0 ms
4.5 ms
6.0 ms
4.5 ms
2.2 ms
1.8 ms
1.8 ms
1.8 ms
0∞C to +70∞C
0∞C to +70∞C
0∞C to +70∞C
DH-32B
DH-32B
DH-32B
DH-32B
DH-32B
DH-32B
DH-32B
DH-32B
DH-32B
DH-32B
DH-32B
–55∞C to +125∞C
–55∞C to +125∞C
–55∞C to +125∞C
–55∞C to +125∞C
0∞C to +70∞C
0∞C to +70∞C
–55∞C to +125∞C
–55∞C to +125∞C
AD578TD
AD578SD/883B
AD578TD/883B
AD579JN
AD579KN
AD579TD
AD579TD/883B
NOTES
1For ±12 V operation Z Version, order AD578ZTD.
2DH = Side Brazed Ceramic DIP.
200ns, min
THEORY OF OPERATION
CONVERT
START
The AD578 is a complete pretrimmed 12-bit ADC that requires
no external components to provide the successive approximation
analog-to-digital conversion function. A block diagram of the
AD578/AD579 is shown in Figure 1.
200ns
80ns
CLOCK
160ns
10ns
100ns
EOC
AD578/AD579
(AD578)
BIT 1
1
2
3
4
5
6
7
8
9
32
–15V
BIT 12
(AD578)
BIT 11
31 +15V
BIT 2
BIT 3
100⍀
20k⍀
30 ANALOG GND
BIT 10
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
20k⍀
5k⍀
29
28
ZERO ADJ
5k⍀
20V SPAN INPUT
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
BIT 9
27 10V SPAN INPUT
10k⍀
26
25
BIPOLAR OFFSET
GAIN (REF IN)
24 REF OUT
BIT 4
BIT 3 10
BIT 2 11
BIT 1 12
BIT 1 13
23 SERIAL OUT
22
SERIAL OUT
21 CONVERT START
20 EOC
SHORT
14
15
19 CLOCK IN
18 CLOCK OUT
17 CLOCK ADJ
CYCLE
DIGITAL
GND
SAR
CLOCK
BIT 10
BIT 11
+5V 16
COMPARATOR
Figure 1. AD578/AD579 Functional Block Diagram and
Pinout
BIT 12
SERIAL
OUT
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12
When the control section is commanded to initiate a conversion,
it enables the clock and resets the successive approximation regis-
ter (SAR). The SAR, timed by the clock, sequences through the
conversion cycle and returns an end-of-convert flag to the control
section. The control section disables the clock and brings the
output status flag low. The data bits are valid on the falling
edge of the clock pulse starting with t1 and ending with t12
(Figures 2a and 2b) and accurately represent the input signal to
within ±1/2 LSB.
CLOCK
INTERNAL: CONNECT CLOCK OUT (18) TO CLOCK IN (19)
EXTERNAL: CONNECT EXTERNAL CLOCK TO CLOCK IN (19)
CLOCK SHOULD BE AT LEAST 30% DUTY CYCLE WITH
MINIMUM PERIOD,T OF 100ns.
MIN
NOTE
THE RISING EDGE OF CONVERT START PULSE RESETS THE MSB TO ZERO,
AND THE LSBs TO ONE.THE TRAILING EDGE INITIATES CONVERSION.
Figure 2a. AD578 Timing Diagram
REV. C
–6–
ADI [ ADI ]
