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5962-01-385-6686 参数 Datasheet PDF下载

5962-01-385-6686图片预览
型号: 5962-01-385-6686
PDF下载: 下载PDF文件 查看货源
内容描述: [IC,A/D CONVERTER,SINGLE,12-BIT,HYBRID,DIP,32PIN]
分类和应用: 光电二极管转换器
文件页数/大小: 12 页 / 368 K
品牌: ADI [ ADI ]
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AD578/AD579  
200ns, min  
UNIPOLAR CALIBRATION  
CONVERT  
START  
CONVERSION TIME  
70ns  
100ns  
The AD578/AD579 are intended to have a nominal 1/2 LSB  
offset so that the exact analog input for a given code will be in  
the middle of that code (halfway between the transitions to the  
codes above and below it). Thus, when properly calibrated, the  
first transition (from 0000 0000 0000 to 0000 0000 0001) will  
occur for an input level of +1/2 LSB.  
125ns  
~15ns  
GATED  
CLOCK  
t1 t2 t3 t4 t5 t6 t7 t8 t9 t10  
t0  
100ns  
CONVERSION IN PROGRESS  
PARALLEL DATA VALID  
EOC  
25ns  
75ns  
BIT 1  
(MSB)  
If Pin 26 is connected to Pin 30, the unit will behave in this  
manner, within specifications. Refer to Table I, Table II, and  
Figure 3 for further clarification. If the offset trim (R1) is used,  
it should be trimmed as above, although a different offset can be  
set for a particular system requirement. This circuit will give  
approximately 25 mV of offset trim range.  
BIT 2  
BIT 3  
BIT 4  
BIT 5  
BIT 6  
BIT 7  
BIT 8  
BIT 9  
BIT 10  
The full-scale trim is done by applying a signal 1 1/2 LSB  
below the nominal full scale. Trim R2 to give the last transition  
(1111 1111 1110 to 1111 1111 11111).  
+15V  
R1  
ZERO ADJ  
10k  
–15V  
0V TO +20V  
20V IN  
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10  
SERIAL  
CLOCK  
ANALOG INPUTS  
BITS 1–12 (AD578)  
10V IN  
BITS 1–10 (AD579)  
0V TO +10V  
INTERNAL: CONNECT CLOCK OUT (18) TO CLOCK IN (19)  
EXTERNAL: CONNECT EXTERNAL CLOCK TO CLOCK IN (19)  
CLOCK SHOULD BE AT LEAST 30% DUTY CYCLE WITH  
AD578/AD579  
MINIMUM PERIOD,T  
OF 100ns.  
MIN  
BIP OFF  
Figure 2b. AD579 Timing Diagram  
CLK OUT  
CLK IN  
REF IN  
The temperature-compensated buried Zener reference provides the  
primary voltage reference to the DAC and guarantees excellent  
stability with both time and temperature. The reference is  
trimmed to 10 V 1.0%; it is buffered and can supply up to  
1 mA to an external load in addition to the current required to  
drive the reference input resistor (0.5 mA) and bipolar offset  
resistor (1 mA). The thin-film application resistors are trimmed  
to match the full-scale output current of the DAC. Two 5 k  
input scaling resistors allow either a 10 V or a 20 V span. The  
10 kbipolar offset resistor is grounded for unipolar operation  
or connected to the 10 V reference for bipolar operation.  
R2  
100⍀  
REF OUT  
+
6.8F  
DIG GND  
ANA GND  
Figure 3. Unipolar Input Connections  
Table I. AD578 Digital Output Codes vs. Analog Input for Unipolar and Bipolar Ranges  
Digital Output Code  
Analog Input—Volts  
(Center of Quantization Interval)  
(Binary for Unipolar Ranges;  
Offset Binary for Bipolar Ranges)  
0 V to +10 V  
Range  
0 V to +20 V  
Range  
–5 V to +5 V  
Range  
–10 V to +10 V  
Range  
B1  
(MSB)  
B12  
(LSB)  
+9.9976  
+19.9951  
+4.9976  
+9.9951  
1 1 1 1 1 1 1 1 1 1 1 1  
+9.9952  
+19.9902  
+4.9952  
+9.9902  
1 1 1 1 1 1 1 1 1 1 1 0  
+5.0024  
+5.0000  
+10.0049  
+10.0000  
+0.0024  
+0.0000  
+0.0049  
+0.0000  
1 0 0 0 0 0 0 0 0 0 0 1  
1 0 0 0 0 0 0 0 0 0 0 0  
+0.0024  
+0.0000  
+0.0051  
+0.0000  
–4.9976  
–5.0000  
–9.9951  
–10.0000  
0 0 0 0 0 0 0 0 0 0 0 1  
0 0 0 0 0 0 0 0 0 0 0 0  
REV. C  
–7–