PAC5225
Power Application Controller
15.3. Functional Description
The PAC clock control system covers a wide range of applications.
15.3.1. Free Running Clock (FRCLK)
The free running clock (FRCLK) is generated from one of the 4 clock sources: ring oscillator, trimmed RC oscillator,
crystal driver or external clock input. The FRCLK is used for the real-time clock (RTC), watchdog timer (WDT), input to
the PLL, or FCLK source to clock the system in low power and sleep mode.
15.3.2. Fast Clock (FCLK)
The fast clock (FCLK) is generated from the PLL or supplied by the FRCLK directly. The FCLK supplies the watchdog
timer (WDT), ADC, wake-up interrupt controller (WIC), SysTick timer, ARM Cortex-M0 peripheral high speed clock
(HCLK) and low speed clock (LSCLK).
15.3.3. High-Speed Clock (HCLK)
The high-speed clock (HCLK) is derived from the FCLK with a /1, /2, /4 or /8 divider. It supplies the peripheral AHB/APB
bus, Timers A to D, dead-time controllers, SPI interface, I2C interface, UART interface, EMUX interface, SOC bridge
interface and memory subsystem, and can go as high as 50MHz.
15.3.4. Auxiliary Clock (ACLK)
The auxiliary clock (ACLK) is derived from FCLK with a /1, /2, to /128 divider, and supplies the timer and dead -time
blocks. It can be clocked faster or slower than HCLK and can go as high as 100MHz.
15.3.5. Clock Gating
The clock tree supports clock gating in deep-sleep mode for the timer block, ADC, SPI interface, I2C interface, UART
interface, memory subsystem and the ARM Cortex-M0 itself.
15.3.6. Ring Oscillator (ROSC)
The integrated ring oscillator provides 4 different clocks with 7.5MHz, 9.6MHz, 13.8MHz, and 25.7MHz settings. After
reset, the clock tree always defaults to this clock input with the lowest frequency setting.
15.3.7. Trimmed 4MHz RC Oscillator
The 1% trimmed 4MHz RC oscillator provides an accurate clock suitable for many applications. It is also used to derive the
clock for the Multi-Mode Power Manager.
15.3.8. Internal Slow RC Oscillator
An internal 32kHz RC oscillator is used during start up to provide an initial clock to analog circuitry. It is not used as a
clock input to the clock tree.
15.3.9. Crystal Oscillator Driver
The optional crystal oscillator driver can drive crystals from 2MHz to 10MHz to provide a highly accurate and stable clock
into the system.
15.3.10. External Clock Input
The clock tree can be supplied with an external clock up to 10MHz.
15.3.11. PLL
The integrated PLL input clock is supplied by the FRCLK with an input frequency range of 1MHz to 25MHz. The PLL
output frequency is adjustable from 3.5MHz to 100MHz.
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Rev 2.0‒September 22, 2017
ACTIVE-SEMI [ ACTIVE-SEMI, INC ]
