PAC5225
Power Application Controller
15. CLOCK CONTROL SYSTEM
15.1. Features
Ring oscillator with 7.5MHz, 9.6MHz, 13.8MHz, and 25.7MHz settings
High accuracy 1% trimmed 4MHz RC oscillator
Crystal oscillator driver supporting 2MHz to 10MHz crystals
External clock input up to 40MHz
PLL with 1MHz to 25 MHz input, and 3.5MHz to 100MHz output
/1 to /8 clock divider for HCLK
/1 to /128 clock divider for ACLK
15.2. Block Diagram
Figure 15-1. Clock Control System
CLOCK CONTROL SYSTEM
FRCLK
FRCLK
DIV
DIV
DIV
DIV
DIV
RTC
WDT
WIC
CLOCK
GATING
ADC
SYSTICK
CORTEX M0
SRAM
CLOCK SOURCES
PPLLL
CLCOLCOKCKTRTEREEE
RING
OSCILLATOR
FLASH
UART
FCLK
HCLK
1% RC
OSCILLATOR
DIV
DIV
DIV
DIV
DIV
CLOCK
GATING
DIVDIV
DIVDIV
PLPLLL
EXTCLK
I2C
XIN
XIN
ACLK
CRYSTAL
DRIVER
XOUT
SOC BUS
SPI
ADC EMUX
TIMERS A, B, C & D
DIV
TIMER
CLOCK
GATING
- 50 -
Rev 2.0‒September 22, 2017
ACTIVE-SEMI [ ACTIVE-SEMI, INC ]
