PAC5225
Power Application Controller
12.4. Electrical Characteristics
Table 26. Gate Drivers Electrical Characteristics
(VP = 12V, VSYS = 5V, and TA = -40°C to 105°C unless otherwise specified.)
UNI
T
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
Low-Side Gate Drivers (DRLx Pins)
VOH,DRL
VOL,DRL
IOHPK,DRL
IOLPK,DRL
High-level output voltage
IDRLx = -50mA
IDRLx = 50mA
10µs pulse
VP−0.5
VP−0.25
V
V
A
A
Low-level output voltage
0.175
-1
0.35
High-level pulsed peak source current
Low-level pulsed peak sink current
10µs pulse
1
High-Side Gate Drivers (DRHx, DRBx and DRSx Pins)
Repetitive, 10µs pulse
Steady state
-5
0
71
70
83
82
16
VDRS
Level-shift driver source voltage range
Bootstrap pin voltage range
V
V
Repetitive, 10µs pulse
Steady state
3
VDRB
5.2
5.2
VBS;DRB
Bootstrap supply voltage range
Bootstrap UVLO threshold
VDRBx, relative to respective VDRSx
V
V
VDRBx rising, relative to respective VDRSx
,hysteresis= 1V
VUVLO;DRB
3.5
4.5
Gate Driver Disabled
Gate Driver Enabled
Gate Driver Disabled
Gate Driver Enabled
23
30
35
45
10
10
IBS;DRB
Bootstrap circuit supply current
Offset supply current
µA
µA
0.5
0.5
IOS;DRB
VDRBx
0.25
-
VOH;DRH
High-level output voltage
Low-level output voltage
IDRHx = -50mA
IDRHx = 50mA
VDRBx−0.6
V
V
VDRSx+0.1
75
VOL;DRH
VDRSx +0.6
IOHPK;DRH
IOLPK;DRH
High-level pulsed peak source current
Low-level pulsed peak sink current
10µs pulse
10µs pulse
-1
1
A
A
High-Side and Low-Side Gate Driver Propagation Delay
Delay setting 00
Delay setting 01
Delay + 0
ns
ns
Delay +
50
tPD
Propagation Delay2
Delay +
100
Delay setting 10
Delay setting 11
ns
ns
Delay +
200
2
Delay from Power Driver Propagation Delay
- 43 -
Rev 2.0‒September 22, 2017
ACTIVE-SEMI [ ACTIVE-SEMI, INC ]
