PAC5225
Power Application Controller
Figure 12-3. High-Side Switching Transients and Optional Circuitry
V
≤ 83V
DRBx
DRBx
V
P
V
IN
DRHx
DRSx
dV/dt
PAC5225
V
V
DRBx
dV/dt
DRLx
DRSx
V
≥ -5V
DRSx
(a) High-Side Switching Transients
(b) Optional Transient Protection and Slew Rate Control
12.3.4. Power Drivers Control
All power drivers are initially disabled from power-on-reset. To enable the power drivers, the microprocessor must first set
the driver enable bit to '1'. The gate drivers are controlled by the microcontroller ports and/or PWM signals according to
Table 24, with configurable delays as shown in Table 25. The OHIx open-drain drivers are controlled by their
corresponding register bits. Refer to the PAC application notes and user guide for additional information on power drivers
control programming.
Table 24. Microcontroller Port and PWM to Power Driver Mapping
PWMA3/
PWMA4/
PWMB0
PART
NUMBER
PWMA5/
PWMC0
PWMA6/
PWMD0
PWMA0
PWMA1
PWMA2
PAC5225
DRL0
DRL1
DRL2
DRH3
DRH4
DRH5
Table 25. Power Driver Propagation Delay
DRLx
DRHx
RISING
FALLING
140ns
RISING
FALLING
140ns
130ns
160ns
12.3.5. Gate Driver Fault Protection
The ASPD incorporates a configurable fault protection mechanism using protection signal from the Configurable Analog
Front End (CAFE), designated as protection event 1 (PR1) signal. The DRL0/DRL1/DRL2 drivers are designated as low-
side group 1. The DRH3/DRH4/DRH5 gate drivers are designated as high-side group 1. The PR1 signal from the CAFE
can be used to disable low-side group 1, high-side group 1, or both depending on the PR1 mask bit settings.
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Rev 2.0‒September 22, 2017
ACTIVE-SEMI [ ACTIVE-SEMI, INC ]
