PAC5225
Power Application Controller
Figure 12-2. Typical Gate Driver Connections
DRBx
V
P
V
IN
DRHx
DRSx
(To loads/inductors.)
DRLx
PAC5225
LOW-SIDE GATE DRIVER
PART
HIGH-SIDE GATE DRIVER
NUMBER
DRLx
SOURCE /SINK CURRENT
DRHx
MAX SUPPLY
SOURCE/ SINK CURRENT
1A/1A
PAC5225
3
1A/1A
3
70V
The ASPD includes built-in configurable fault protection for the internal gate drivers.
12.3.1. Low-Side Gate Driver
The DRLx low-side gate driver drives the gate of an external MOSFET or IGBT switch between the low-level VSSP power
ground rail and high-level VP supply rail. The DRLx output pin has sink and source output current capability of 1A. Each
low-side gate driver is controlled by a microcontroller port signal with 4 configurable levels of propagation delay.
12.3.2. High-Side Gate Driver
The DRHx high-side gate driver drives the gate of an external MOSFET or IGBT switch between its low-level DRSx driver
source rail and its high-level DRBx bootstrap rail. The DRSx pin can go up to 70V steady state. The DRHx output pin has
sink and source output current capability of 1A. The DRBx bootstrap pin can have a maximum operating voltage of 16V
relative to the DRSx pin, and up to 82V steady state. The DRSx pin is designed to tolerate momentary switching negative
spikes down to -5V without affecting the DRHx output state. Each high-side gate driver is controlled by a microcontroller
port signal with 4 configurable levels of propagation delay.
For bootstrapped high-side operation, connect an appropriate capacitor between DRBx and DRSx and a properly rated
bootstrap diode from VP to DRBx. To operate the DRHx output as a low-side gate driver, connect its DRBx pin to VP and its
DRSx pin to VSSP
.
12.3.3. High-Side Switching Transients
Typical high-side switching transients are shown in Figure 12-3(a). To ensure functionality and reliability, the DRSx and
DRBx pins must not exceed the peak and undershoot limit values shown. This should be verified by probing the DRBx and
DRSx pins directly relative to VSS pin. A small resistor and diode clamp for the DRSx pin can be used to make sure that
the pin voltage stays within the negative limit value. In addition, the high-side slew rate dV/dt must be kept within ±5V/ns
for DRSx. This can be achieved by adding a resistor-diode pair in series, and an optional capacitor in parallel with the
power switch gate. The parallel capacitor also provides a low impedance and close gate shunt against coupling from the
switch drain. These optional protection and slew rate control are shown in Figure 12-3(b).
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Rev 2.0‒September 22, 2017
ACTIVE-SEMI [ ACTIVE-SEMI, INC ]
